xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll (revision b6c0f1bfa79a3a32d841ac5ab1f94c3aee3b5d90) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s
3; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s
4
5declare <2 x i7> @llvm.vp.trunc.v2i7.v2i16(<2 x i16>, <2 x i1>, i32)
6
7define <2 x i7> @vtrunc_v2i7_v2i16(<2 x i16> %a, <2 x i1> %m, i32 zeroext %vl) {
8; CHECK-LABEL: vtrunc_v2i7_v2i16:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
11; CHECK-NEXT:    vnsrl.wi v8, v8, 0, v0.t
12; CHECK-NEXT:    ret
13  %v = call <2 x i7> @llvm.vp.trunc.v2i7.v2i16(<2 x i16> %a, <2 x i1> %m, i32 %vl)
14  ret <2 x i7> %v
15}
16
17declare <2 x i8> @llvm.vp.trunc.v2i8.v2i15(<2 x i15>, <2 x i1>, i32)
18
19define <2 x i8> @vtrunc_v2i8_v2i15(<2 x i15> %a, <2 x i1> %m, i32 zeroext %vl) {
20; CHECK-LABEL: vtrunc_v2i8_v2i15:
21; CHECK:       # %bb.0:
22; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
23; CHECK-NEXT:    vnsrl.wi v8, v8, 0, v0.t
24; CHECK-NEXT:    ret
25  %v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i15(<2 x i15> %a, <2 x i1> %m, i32 %vl)
26  ret <2 x i8> %v
27}
28
29declare <2 x i8> @llvm.vp.trunc.v2i8.v2i16(<2 x i16>, <2 x i1>, i32)
30
31define <2 x i8> @vtrunc_v2i8_v2i16(<2 x i16> %a, <2 x i1> %m, i32 zeroext %vl) {
32; CHECK-LABEL: vtrunc_v2i8_v2i16:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
35; CHECK-NEXT:    vnsrl.wi v8, v8, 0, v0.t
36; CHECK-NEXT:    ret
37  %v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i16(<2 x i16> %a, <2 x i1> %m, i32 %vl)
38  ret <2 x i8> %v
39}
40
41define <2 x i8> @vtrunc_v2i8_v2i16_unmasked(<2 x i16> %a, i32 zeroext %vl) {
42; CHECK-LABEL: vtrunc_v2i8_v2i16_unmasked:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
45; CHECK-NEXT:    vnsrl.wi v8, v8, 0
46; CHECK-NEXT:    ret
47  %v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i16(<2 x i16> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)
48  ret <2 x i8> %v
49}
50
51declare <128 x i7> @llvm.vp.trunc.v128i7.v128i16(<128 x i16>, <128 x i1>, i32)
52
53define <128 x i7> @vtrunc_v128i7_v128i16(<128 x i16> %a, <128 x i1> %m, i32 zeroext %vl) {
54; CHECK-LABEL: vtrunc_v128i7_v128i16:
55; CHECK:       # %bb.0:
56; CHECK-NEXT:    vsetivli zero, 8, e8, m1, ta, ma
57; CHECK-NEXT:    vmv8r.v v24, v8
58; CHECK-NEXT:    li a1, 64
59; CHECK-NEXT:    vslidedown.vi v12, v0, 8
60; CHECK-NEXT:    mv a2, a0
61; CHECK-NEXT:    bltu a0, a1, .LBB4_2
62; CHECK-NEXT:  # %bb.1:
63; CHECK-NEXT:    li a2, 64
64; CHECK-NEXT:  .LBB4_2:
65; CHECK-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
66; CHECK-NEXT:    vnsrl.wi v8, v24, 0, v0.t
67; CHECK-NEXT:    addi a2, a0, -64
68; CHECK-NEXT:    sltu a0, a0, a2
69; CHECK-NEXT:    addi a0, a0, -1
70; CHECK-NEXT:    and a0, a0, a2
71; CHECK-NEXT:    vmv1r.v v0, v12
72; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
73; CHECK-NEXT:    vnsrl.wi v24, v16, 0, v0.t
74; CHECK-NEXT:    li a0, 128
75; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
76; CHECK-NEXT:    vslideup.vx v8, v24, a1
77; CHECK-NEXT:    ret
78  %v = call <128 x i7> @llvm.vp.trunc.v128i7.v128i16(<128 x i16> %a, <128 x i1> %m, i32 %vl)
79  ret <128 x i7> %v
80}
81
82declare <2 x i8> @llvm.vp.trunc.v2i8.v2i32(<2 x i32>, <2 x i1>, i32)
83
84define <2 x i8> @vtrunc_v2i8_v2i32(<2 x i32> %a, <2 x i1> %m, i32 zeroext %vl) {
85; CHECK-LABEL: vtrunc_v2i8_v2i32:
86; CHECK:       # %bb.0:
87; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
88; CHECK-NEXT:    vnsrl.wi v8, v8, 0, v0.t
89; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
90; CHECK-NEXT:    vnsrl.wi v8, v8, 0, v0.t
91; CHECK-NEXT:    ret
92  %v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i32(<2 x i32> %a, <2 x i1> %m, i32 %vl)
93  ret <2 x i8> %v
94}
95
96define <2 x i8> @vtrunc_v2i8_v2i32_unmasked(<2 x i32> %a, i32 zeroext %vl) {
97; CHECK-LABEL: vtrunc_v2i8_v2i32_unmasked:
98; CHECK:       # %bb.0:
99; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
100; CHECK-NEXT:    vnsrl.wi v8, v8, 0
101; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
102; CHECK-NEXT:    vnsrl.wi v8, v8, 0
103; CHECK-NEXT:    ret
104  %v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i32(<2 x i32> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)
105  ret <2 x i8> %v
106}
107
108declare <2 x i8> @llvm.vp.trunc.v2i8.v2i64(<2 x i64>, <2 x i1>, i32)
109
110define <2 x i8> @vtrunc_v2i8_v2i64(<2 x i64> %a, <2 x i1> %m, i32 zeroext %vl) {
111; CHECK-LABEL: vtrunc_v2i8_v2i64:
112; CHECK:       # %bb.0:
113; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
114; CHECK-NEXT:    vnsrl.wi v8, v8, 0, v0.t
115; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
116; CHECK-NEXT:    vnsrl.wi v8, v8, 0, v0.t
117; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
118; CHECK-NEXT:    vnsrl.wi v8, v8, 0, v0.t
119; CHECK-NEXT:    ret
120  %v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i64(<2 x i64> %a, <2 x i1> %m, i32 %vl)
121  ret <2 x i8> %v
122}
123
124define <2 x i8> @vtrunc_v2i8_v2i64_unmasked(<2 x i64> %a, i32 zeroext %vl) {
125; CHECK-LABEL: vtrunc_v2i8_v2i64_unmasked:
126; CHECK:       # %bb.0:
127; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
128; CHECK-NEXT:    vnsrl.wi v8, v8, 0
129; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
130; CHECK-NEXT:    vnsrl.wi v8, v8, 0
131; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
132; CHECK-NEXT:    vnsrl.wi v8, v8, 0
133; CHECK-NEXT:    ret
134  %v = call <2 x i8> @llvm.vp.trunc.v2i8.v2i64(<2 x i64> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)
135  ret <2 x i8> %v
136}
137
138declare <2 x i16> @llvm.vp.trunc.v2i16.v2i32(<2 x i32>, <2 x i1>, i32)
139
140define <2 x i16> @vtrunc_v2i16_v2i32(<2 x i32> %a, <2 x i1> %m, i32 zeroext %vl) {
141; CHECK-LABEL: vtrunc_v2i16_v2i32:
142; CHECK:       # %bb.0:
143; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
144; CHECK-NEXT:    vnsrl.wi v8, v8, 0, v0.t
145; CHECK-NEXT:    ret
146  %v = call <2 x i16> @llvm.vp.trunc.v2i16.v2i32(<2 x i32> %a, <2 x i1> %m, i32 %vl)
147  ret <2 x i16> %v
148}
149
150define <2 x i16> @vtrunc_v2i16_v2i32_unmasked(<2 x i32> %a, i32 zeroext %vl) {
151; CHECK-LABEL: vtrunc_v2i16_v2i32_unmasked:
152; CHECK:       # %bb.0:
153; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
154; CHECK-NEXT:    vnsrl.wi v8, v8, 0
155; CHECK-NEXT:    ret
156  %v = call <2 x i16> @llvm.vp.trunc.v2i16.v2i32(<2 x i32> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)
157  ret <2 x i16> %v
158}
159
160declare <2 x i16> @llvm.vp.trunc.v2i16.v2i64(<2 x i64>, <2 x i1>, i32)
161
162define <2 x i16> @vtrunc_v2i16_v2i64(<2 x i64> %a, <2 x i1> %m, i32 zeroext %vl) {
163; CHECK-LABEL: vtrunc_v2i16_v2i64:
164; CHECK:       # %bb.0:
165; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
166; CHECK-NEXT:    vnsrl.wi v8, v8, 0, v0.t
167; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
168; CHECK-NEXT:    vnsrl.wi v8, v8, 0, v0.t
169; CHECK-NEXT:    ret
170  %v = call <2 x i16> @llvm.vp.trunc.v2i16.v2i64(<2 x i64> %a, <2 x i1> %m, i32 %vl)
171  ret <2 x i16> %v
172}
173
174define <2 x i16> @vtrunc_v2i16_v2i64_unmasked(<2 x i64> %a, i32 zeroext %vl) {
175; CHECK-LABEL: vtrunc_v2i16_v2i64_unmasked:
176; CHECK:       # %bb.0:
177; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
178; CHECK-NEXT:    vnsrl.wi v8, v8, 0
179; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
180; CHECK-NEXT:    vnsrl.wi v8, v8, 0
181; CHECK-NEXT:    ret
182  %v = call <2 x i16> @llvm.vp.trunc.v2i16.v2i64(<2 x i64> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)
183  ret <2 x i16> %v
184}
185
186declare <15 x i16> @llvm.vp.trunc.v15i16.v15i64(<15 x i64>, <15 x i1>, i32)
187
188define <15 x i16> @vtrunc_v15i16_v15i64(<15 x i64> %a, <15 x i1> %m, i32 zeroext %vl) {
189; CHECK-LABEL: vtrunc_v15i16_v15i64:
190; CHECK:       # %bb.0:
191; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
192; CHECK-NEXT:    vnsrl.wi v16, v8, 0, v0.t
193; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
194; CHECK-NEXT:    vnsrl.wi v8, v16, 0, v0.t
195; CHECK-NEXT:    ret
196  %v = call <15 x i16> @llvm.vp.trunc.v15i16.v15i64(<15 x i64> %a, <15 x i1> %m, i32 %vl)
197  ret <15 x i16> %v
198}
199
200declare <2 x i32> @llvm.vp.trunc.v2i32.v2i64(<2 x i64>, <2 x i1>, i32)
201
202define <2 x i32> @vtrunc_v2i32_v2i64(<2 x i64> %a, <2 x i1> %m, i32 zeroext %vl) {
203; CHECK-LABEL: vtrunc_v2i32_v2i64:
204; CHECK:       # %bb.0:
205; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
206; CHECK-NEXT:    vnsrl.wi v8, v8, 0, v0.t
207; CHECK-NEXT:    ret
208  %v = call <2 x i32> @llvm.vp.trunc.v2i32.v2i64(<2 x i64> %a, <2 x i1> %m, i32 %vl)
209  ret <2 x i32> %v
210}
211
212define <2 x i32> @vtrunc_v2i32_v2i64_unmasked(<2 x i64> %a, i32 zeroext %vl) {
213; CHECK-LABEL: vtrunc_v2i32_v2i64_unmasked:
214; CHECK:       # %bb.0:
215; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
216; CHECK-NEXT:    vnsrl.wi v8, v8, 0
217; CHECK-NEXT:    ret
218  %v = call <2 x i32> @llvm.vp.trunc.v2i32.v2i64(<2 x i64> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)
219  ret <2 x i32> %v
220}
221
222declare <128 x i32> @llvm.vp.trunc.v128i32.v128i64(<128 x i64>, <128 x i1>, i32)
223
224define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 zeroext %vl) {
225; CHECK-LABEL: vtrunc_v128i32_v128i64:
226; CHECK:       # %bb.0:
227; CHECK-NEXT:    addi sp, sp, -16
228; CHECK-NEXT:    .cfi_def_cfa_offset 16
229; CHECK-NEXT:    csrr a2, vlenb
230; CHECK-NEXT:    li a3, 72
231; CHECK-NEXT:    mul a2, a2, a3
232; CHECK-NEXT:    sub sp, sp, a2
233; CHECK-NEXT:    .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xc8, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 72 * vlenb
234; CHECK-NEXT:    vsetivli zero, 8, e8, m1, ta, ma
235; CHECK-NEXT:    vmv1r.v v7, v0
236; CHECK-NEXT:    csrr a2, vlenb
237; CHECK-NEXT:    li a3, 24
238; CHECK-NEXT:    mul a2, a2, a3
239; CHECK-NEXT:    add a2, sp, a2
240; CHECK-NEXT:    addi a2, a2, 16
241; CHECK-NEXT:    vs8r.v v16, (a2) # Unknown-size Folded Spill
242; CHECK-NEXT:    csrr a2, vlenb
243; CHECK-NEXT:    slli a2, a2, 5
244; CHECK-NEXT:    add a2, sp, a2
245; CHECK-NEXT:    addi a2, a2, 16
246; CHECK-NEXT:    vs8r.v v8, (a2) # Unknown-size Folded Spill
247; CHECK-NEXT:    vslidedown.vi v6, v0, 8
248; CHECK-NEXT:    addi a2, a1, 512
249; CHECK-NEXT:    addi a3, a1, 640
250; CHECK-NEXT:    addi a4, a7, -64
251; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma
252; CHECK-NEXT:    vslidedown.vi v27, v6, 4
253; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
254; CHECK-NEXT:    vle64.v v8, (a3)
255; CHECK-NEXT:    sltu a3, a7, a4
256; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
257; CHECK-NEXT:    vslidedown.vi v0, v27, 2
258; CHECK-NEXT:    addi a3, a3, -1
259; CHECK-NEXT:    and a4, a3, a4
260; CHECK-NEXT:    addi a3, a4, -32
261; CHECK-NEXT:    sltu a5, a4, a3
262; CHECK-NEXT:    addi a5, a5, -1
263; CHECK-NEXT:    and a3, a5, a3
264; CHECK-NEXT:    addi a5, a3, -16
265; CHECK-NEXT:    sltu a6, a3, a5
266; CHECK-NEXT:    addi a6, a6, -1
267; CHECK-NEXT:    and a5, a6, a5
268; CHECK-NEXT:    vsetvli zero, a5, e32, m4, ta, ma
269; CHECK-NEXT:    vnsrl.wi v16, v8, 0, v0.t
270; CHECK-NEXT:    csrr a5, vlenb
271; CHECK-NEXT:    slli a5, a5, 4
272; CHECK-NEXT:    add a5, sp, a5
273; CHECK-NEXT:    addi a5, a5, 16
274; CHECK-NEXT:    vs8r.v v16, (a5) # Unknown-size Folded Spill
275; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
276; CHECK-NEXT:    vle64.v v8, (a2)
277; CHECK-NEXT:    addi a5, a1, 128
278; CHECK-NEXT:    li a2, 16
279; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma
280; CHECK-NEXT:    vslidedown.vi v26, v7, 4
281; CHECK-NEXT:    bltu a3, a2, .LBB16_2
282; CHECK-NEXT:  # %bb.1:
283; CHECK-NEXT:    li a3, 16
284; CHECK-NEXT:  .LBB16_2:
285; CHECK-NEXT:    vmv1r.v v0, v27
286; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
287; CHECK-NEXT:    vle64.v v16, (a5)
288; CHECK-NEXT:    csrr a5, vlenb
289; CHECK-NEXT:    li a6, 56
290; CHECK-NEXT:    mul a5, a5, a6
291; CHECK-NEXT:    add a5, sp, a5
292; CHECK-NEXT:    addi a5, a5, 16
293; CHECK-NEXT:    vs8r.v v16, (a5) # Unknown-size Folded Spill
294; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
295; CHECK-NEXT:    vslidedown.vi v27, v26, 2
296; CHECK-NEXT:    li a5, 64
297; CHECK-NEXT:    vsetvli zero, a3, e32, m4, ta, ma
298; CHECK-NEXT:    vnsrl.wi v16, v8, 0, v0.t
299; CHECK-NEXT:    csrr a3, vlenb
300; CHECK-NEXT:    slli a3, a3, 6
301; CHECK-NEXT:    add a3, sp, a3
302; CHECK-NEXT:    addi a3, a3, 16
303; CHECK-NEXT:    vs8r.v v16, (a3) # Unknown-size Folded Spill
304; CHECK-NEXT:    mv a6, a7
305; CHECK-NEXT:    bltu a7, a5, .LBB16_4
306; CHECK-NEXT:  # %bb.3:
307; CHECK-NEXT:    li a6, 64
308; CHECK-NEXT:  .LBB16_4:
309; CHECK-NEXT:    vmv1r.v v0, v27
310; CHECK-NEXT:    addi a5, a1, 384
311; CHECK-NEXT:    li a3, 32
312; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
313; CHECK-NEXT:    vle64.v v8, (a1)
314; CHECK-NEXT:    csrr t0, vlenb
315; CHECK-NEXT:    li t1, 48
316; CHECK-NEXT:    mul t0, t0, t1
317; CHECK-NEXT:    add t0, sp, t0
318; CHECK-NEXT:    addi t0, t0, 16
319; CHECK-NEXT:    vs8r.v v8, (t0) # Unknown-size Folded Spill
320; CHECK-NEXT:    addi t0, a6, -32
321; CHECK-NEXT:    sltu a6, a6, t0
322; CHECK-NEXT:    addi a6, a6, -1
323; CHECK-NEXT:    and a6, a6, t0
324; CHECK-NEXT:    addi t0, a6, -16
325; CHECK-NEXT:    sltu t1, a6, t0
326; CHECK-NEXT:    addi t1, t1, -1
327; CHECK-NEXT:    and t0, t1, t0
328; CHECK-NEXT:    csrr t1, vlenb
329; CHECK-NEXT:    li t2, 56
330; CHECK-NEXT:    mul t1, t1, t2
331; CHECK-NEXT:    add t1, sp, t1
332; CHECK-NEXT:    addi t1, t1, 16
333; CHECK-NEXT:    vl8r.v v16, (t1) # Unknown-size Folded Reload
334; CHECK-NEXT:    vsetvli zero, t0, e32, m4, ta, ma
335; CHECK-NEXT:    vnsrl.wi v8, v16, 0, v0.t
336; CHECK-NEXT:    csrr t0, vlenb
337; CHECK-NEXT:    slli t0, t0, 3
338; CHECK-NEXT:    add t0, sp, t0
339; CHECK-NEXT:    addi t0, t0, 16
340; CHECK-NEXT:    vs8r.v v8, (t0) # Unknown-size Folded Spill
341; CHECK-NEXT:    bltu a6, a2, .LBB16_6
342; CHECK-NEXT:  # %bb.5:
343; CHECK-NEXT:    li a6, 16
344; CHECK-NEXT:  .LBB16_6:
345; CHECK-NEXT:    vmv1r.v v0, v26
346; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
347; CHECK-NEXT:    vle64.v v8, (a5)
348; CHECK-NEXT:    addi a5, sp, 16
349; CHECK-NEXT:    vs8r.v v8, (a5) # Unknown-size Folded Spill
350; CHECK-NEXT:    addi a1, a1, 256
351; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
352; CHECK-NEXT:    vslidedown.vi v26, v6, 2
353; CHECK-NEXT:    csrr a5, vlenb
354; CHECK-NEXT:    li t0, 48
355; CHECK-NEXT:    mul a5, a5, t0
356; CHECK-NEXT:    add a5, sp, a5
357; CHECK-NEXT:    addi a5, a5, 16
358; CHECK-NEXT:    vl8r.v v16, (a5) # Unknown-size Folded Reload
359; CHECK-NEXT:    vsetvli zero, a6, e32, m4, ta, ma
360; CHECK-NEXT:    vnsrl.wi v8, v16, 0, v0.t
361; CHECK-NEXT:    csrr a5, vlenb
362; CHECK-NEXT:    li a6, 56
363; CHECK-NEXT:    mul a5, a5, a6
364; CHECK-NEXT:    add a5, sp, a5
365; CHECK-NEXT:    addi a5, a5, 16
366; CHECK-NEXT:    vs8r.v v8, (a5) # Unknown-size Folded Spill
367; CHECK-NEXT:    mv a5, a4
368; CHECK-NEXT:    bltu a4, a3, .LBB16_8
369; CHECK-NEXT:  # %bb.7:
370; CHECK-NEXT:    li a5, 32
371; CHECK-NEXT:  .LBB16_8:
372; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
373; CHECK-NEXT:    vle64.v v16, (a1)
374; CHECK-NEXT:    addi a1, a5, -16
375; CHECK-NEXT:    sltu a5, a5, a1
376; CHECK-NEXT:    addi a5, a5, -1
377; CHECK-NEXT:    and a1, a5, a1
378; CHECK-NEXT:    vmv1r.v v0, v26
379; CHECK-NEXT:    addi a5, sp, 16
380; CHECK-NEXT:    vl8r.v v24, (a5) # Unknown-size Folded Reload
381; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
382; CHECK-NEXT:    vnsrl.wi v8, v24, 0, v0.t
383; CHECK-NEXT:    csrr a1, vlenb
384; CHECK-NEXT:    li a5, 40
385; CHECK-NEXT:    mul a1, a1, a5
386; CHECK-NEXT:    add a1, sp, a1
387; CHECK-NEXT:    addi a1, a1, 16
388; CHECK-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
389; CHECK-NEXT:    bltu a4, a2, .LBB16_10
390; CHECK-NEXT:  # %bb.9:
391; CHECK-NEXT:    li a4, 16
392; CHECK-NEXT:  .LBB16_10:
393; CHECK-NEXT:    vmv1r.v v0, v6
394; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
395; CHECK-NEXT:    vslidedown.vi v25, v7, 2
396; CHECK-NEXT:    vsetvli zero, a4, e32, m4, ta, ma
397; CHECK-NEXT:    vnsrl.wi v8, v16, 0, v0.t
398; CHECK-NEXT:    csrr a1, vlenb
399; CHECK-NEXT:    li a4, 48
400; CHECK-NEXT:    mul a1, a1, a4
401; CHECK-NEXT:    add a1, sp, a1
402; CHECK-NEXT:    addi a1, a1, 16
403; CHECK-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
404; CHECK-NEXT:    mv a1, a7
405; CHECK-NEXT:    bltu a7, a3, .LBB16_12
406; CHECK-NEXT:  # %bb.11:
407; CHECK-NEXT:    li a1, 32
408; CHECK-NEXT:  .LBB16_12:
409; CHECK-NEXT:    vmv1r.v v0, v25
410; CHECK-NEXT:    csrr a4, vlenb
411; CHECK-NEXT:    slli a4, a4, 4
412; CHECK-NEXT:    add a4, sp, a4
413; CHECK-NEXT:    addi a4, a4, 16
414; CHECK-NEXT:    vl8r.v v16, (a4) # Unknown-size Folded Reload
415; CHECK-NEXT:    vmv4r.v v24, v16
416; CHECK-NEXT:    csrr a4, vlenb
417; CHECK-NEXT:    slli a4, a4, 3
418; CHECK-NEXT:    add a4, sp, a4
419; CHECK-NEXT:    addi a4, a4, 16
420; CHECK-NEXT:    vl8r.v v8, (a4) # Unknown-size Folded Reload
421; CHECK-NEXT:    csrr a4, vlenb
422; CHECK-NEXT:    li a5, 40
423; CHECK-NEXT:    mul a4, a4, a5
424; CHECK-NEXT:    add a4, sp, a4
425; CHECK-NEXT:    addi a4, a4, 16
426; CHECK-NEXT:    vl8r.v v16, (a4) # Unknown-size Folded Reload
427; CHECK-NEXT:    csrr a4, vlenb
428; CHECK-NEXT:    li a5, 40
429; CHECK-NEXT:    mul a4, a4, a5
430; CHECK-NEXT:    add a4, sp, a4
431; CHECK-NEXT:    addi a4, a4, 16
432; CHECK-NEXT:    vs8r.v v16, (a4) # Unknown-size Folded Spill
433; CHECK-NEXT:    csrr a4, vlenb
434; CHECK-NEXT:    slli a4, a4, 6
435; CHECK-NEXT:    add a4, sp, a4
436; CHECK-NEXT:    addi a4, a4, 16
437; CHECK-NEXT:    vl8r.v v16, (a4) # Unknown-size Folded Reload
438; CHECK-NEXT:    vsetvli zero, a3, e32, m8, ta, ma
439; CHECK-NEXT:    vslideup.vi v16, v24, 16
440; CHECK-NEXT:    csrr a4, vlenb
441; CHECK-NEXT:    slli a4, a4, 6
442; CHECK-NEXT:    add a4, sp, a4
443; CHECK-NEXT:    addi a4, a4, 16
444; CHECK-NEXT:    vs8r.v v16, (a4) # Unknown-size Folded Spill
445; CHECK-NEXT:    addi a4, a1, -16
446; CHECK-NEXT:    csrr a5, vlenb
447; CHECK-NEXT:    li a6, 56
448; CHECK-NEXT:    mul a5, a5, a6
449; CHECK-NEXT:    add a5, sp, a5
450; CHECK-NEXT:    addi a5, a5, 16
451; CHECK-NEXT:    vl8r.v v16, (a5) # Unknown-size Folded Reload
452; CHECK-NEXT:    vslideup.vi v16, v8, 16
453; CHECK-NEXT:    csrr a5, vlenb
454; CHECK-NEXT:    li a6, 56
455; CHECK-NEXT:    mul a5, a5, a6
456; CHECK-NEXT:    add a5, sp, a5
457; CHECK-NEXT:    addi a5, a5, 16
458; CHECK-NEXT:    vs8r.v v16, (a5) # Unknown-size Folded Spill
459; CHECK-NEXT:    csrr a5, vlenb
460; CHECK-NEXT:    li a6, 48
461; CHECK-NEXT:    mul a5, a5, a6
462; CHECK-NEXT:    add a5, sp, a5
463; CHECK-NEXT:    addi a5, a5, 16
464; CHECK-NEXT:    vl8r.v v8, (a5) # Unknown-size Folded Reload
465; CHECK-NEXT:    csrr a5, vlenb
466; CHECK-NEXT:    li a6, 40
467; CHECK-NEXT:    mul a5, a5, a6
468; CHECK-NEXT:    add a5, sp, a5
469; CHECK-NEXT:    addi a5, a5, 16
470; CHECK-NEXT:    vl8r.v v16, (a5) # Unknown-size Folded Reload
471; CHECK-NEXT:    vslideup.vi v8, v16, 16
472; CHECK-NEXT:    csrr a5, vlenb
473; CHECK-NEXT:    li a6, 48
474; CHECK-NEXT:    mul a5, a5, a6
475; CHECK-NEXT:    add a5, sp, a5
476; CHECK-NEXT:    addi a5, a5, 16
477; CHECK-NEXT:    vs8r.v v8, (a5) # Unknown-size Folded Spill
478; CHECK-NEXT:    sltu a1, a1, a4
479; CHECK-NEXT:    addi a1, a1, -1
480; CHECK-NEXT:    and a1, a1, a4
481; CHECK-NEXT:    csrr a4, vlenb
482; CHECK-NEXT:    li a5, 24
483; CHECK-NEXT:    mul a4, a4, a5
484; CHECK-NEXT:    add a4, sp, a4
485; CHECK-NEXT:    addi a4, a4, 16
486; CHECK-NEXT:    vl8r.v v16, (a4) # Unknown-size Folded Reload
487; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
488; CHECK-NEXT:    vnsrl.wi v8, v16, 0, v0.t
489; CHECK-NEXT:    bltu a7, a2, .LBB16_14
490; CHECK-NEXT:  # %bb.13:
491; CHECK-NEXT:    li a7, 16
492; CHECK-NEXT:  .LBB16_14:
493; CHECK-NEXT:    vmv1r.v v0, v7
494; CHECK-NEXT:    csrr a1, vlenb
495; CHECK-NEXT:    slli a1, a1, 5
496; CHECK-NEXT:    add a1, sp, a1
497; CHECK-NEXT:    addi a1, a1, 16
498; CHECK-NEXT:    vl8r.v v16, (a1) # Unknown-size Folded Reload
499; CHECK-NEXT:    vsetvli zero, a7, e32, m4, ta, ma
500; CHECK-NEXT:    vnsrl.wi v24, v16, 0, v0.t
501; CHECK-NEXT:    vsetvli zero, a3, e32, m8, ta, ma
502; CHECK-NEXT:    vslideup.vi v24, v8, 16
503; CHECK-NEXT:    vse32.v v24, (a0)
504; CHECK-NEXT:    addi a1, a0, 256
505; CHECK-NEXT:    csrr a2, vlenb
506; CHECK-NEXT:    li a3, 48
507; CHECK-NEXT:    mul a2, a2, a3
508; CHECK-NEXT:    add a2, sp, a2
509; CHECK-NEXT:    addi a2, a2, 16
510; CHECK-NEXT:    vl8r.v v8, (a2) # Unknown-size Folded Reload
511; CHECK-NEXT:    vse32.v v8, (a1)
512; CHECK-NEXT:    addi a1, a0, 128
513; CHECK-NEXT:    csrr a2, vlenb
514; CHECK-NEXT:    li a3, 56
515; CHECK-NEXT:    mul a2, a2, a3
516; CHECK-NEXT:    add a2, sp, a2
517; CHECK-NEXT:    addi a2, a2, 16
518; CHECK-NEXT:    vl8r.v v8, (a2) # Unknown-size Folded Reload
519; CHECK-NEXT:    vse32.v v8, (a1)
520; CHECK-NEXT:    addi a0, a0, 384
521; CHECK-NEXT:    csrr a1, vlenb
522; CHECK-NEXT:    slli a1, a1, 6
523; CHECK-NEXT:    add a1, sp, a1
524; CHECK-NEXT:    addi a1, a1, 16
525; CHECK-NEXT:    vl8r.v v8, (a1) # Unknown-size Folded Reload
526; CHECK-NEXT:    vse32.v v8, (a0)
527; CHECK-NEXT:    csrr a0, vlenb
528; CHECK-NEXT:    li a1, 72
529; CHECK-NEXT:    mul a0, a0, a1
530; CHECK-NEXT:    add sp, sp, a0
531; CHECK-NEXT:    .cfi_def_cfa sp, 16
532; CHECK-NEXT:    addi sp, sp, 16
533; CHECK-NEXT:    .cfi_def_cfa_offset 0
534; CHECK-NEXT:    ret
535  %v = call <128 x i32> @llvm.vp.trunc.v128i32.v128i64(<128 x i64> %a, <128 x i1> %m, i32 %vl)
536  ret <128 x i32> %v
537}
538
539declare <32 x i32> @llvm.vp.trunc.v32i32.v32i64(<32 x i64>, <32 x i1>, i32)
540
541define <32 x i32> @vtrunc_v32i32_v32i64(<32 x i64> %a, <32 x i1> %m, i32 zeroext %vl) {
542; CHECK-LABEL: vtrunc_v32i32_v32i64:
543; CHECK:       # %bb.0:
544; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
545; CHECK-NEXT:    vmv8r.v v24, v8
546; CHECK-NEXT:    li a2, 16
547; CHECK-NEXT:    vslidedown.vi v12, v0, 2
548; CHECK-NEXT:    mv a1, a0
549; CHECK-NEXT:    bltu a0, a2, .LBB17_2
550; CHECK-NEXT:  # %bb.1:
551; CHECK-NEXT:    li a1, 16
552; CHECK-NEXT:  .LBB17_2:
553; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
554; CHECK-NEXT:    vnsrl.wi v8, v24, 0, v0.t
555; CHECK-NEXT:    addi a1, a0, -16
556; CHECK-NEXT:    sltu a0, a0, a1
557; CHECK-NEXT:    addi a0, a0, -1
558; CHECK-NEXT:    and a0, a0, a1
559; CHECK-NEXT:    vmv1r.v v0, v12
560; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
561; CHECK-NEXT:    vnsrl.wi v24, v16, 0, v0.t
562; CHECK-NEXT:    li a0, 32
563; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
564; CHECK-NEXT:    vslideup.vi v8, v24, 16
565; CHECK-NEXT:    ret
566  %v = call <32 x i32> @llvm.vp.trunc.v32i32.v32i64(<32 x i64> %a, <32 x i1> %m, i32 %vl)
567  ret <32 x i32> %v
568}
569
570declare <2 x i7> @llvm.vp.trunc.v2i7.v2i8(<2 x i8>, <2 x i1>, i32)
571
572define <2 x i7> @vtrunc_v2i7_v2i8(<2 x i8> %a, <2 x i1> %m, i32 zeroext %vl) {
573; CHECK-LABEL: vtrunc_v2i7_v2i8:
574; CHECK:       # %bb.0:
575; CHECK-NEXT:    ret
576  %v = call <2 x i7> @llvm.vp.trunc.v2i7.v2i8(<2 x i8> %a, <2 x i1> %m, i32 %vl)
577  ret <2 x i7> %v
578}
579