xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp-mask.ll (revision 74f985b793bf4005e49736f8c2cef8b5cbf7c1ab) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
4
5declare <2 x i1> @llvm.vp.trunc.v2i1.v2i16(<2 x i16>, <2 x i1>, i32)
6
7define <2 x i1> @vtrunc_v2i1_v2i16(<2 x i16> %a, <2 x i1> %m, i32 zeroext %vl) {
8; CHECK-LABEL: vtrunc_v2i1_v2i16:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
11; CHECK-NEXT:    vand.vi v8, v8, 1, v0.t
12; CHECK-NEXT:    vmsne.vi v0, v8, 0, v0.t
13; CHECK-NEXT:    ret
14  %v = call <2 x i1> @llvm.vp.trunc.v2i1.v2i16(<2 x i16> %a, <2 x i1> %m, i32 %vl)
15  ret <2 x i1> %v
16}
17
18define <2 x i1> @vtrunc_v2i1_v2i16_unmasked(<2 x i16> %a, i32 zeroext %vl) {
19; CHECK-LABEL: vtrunc_v2i1_v2i16_unmasked:
20; CHECK:       # %bb.0:
21; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
22; CHECK-NEXT:    vand.vi v8, v8, 1
23; CHECK-NEXT:    vmsne.vi v0, v8, 0
24; CHECK-NEXT:    ret
25  %v = call <2 x i1> @llvm.vp.trunc.v2i1.v2i16(<2 x i16> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)
26  ret <2 x i1> %v
27}
28
29declare <2 x i1> @llvm.vp.trunc.v2i1.v2i32(<2 x i32>, <2 x i1>, i32)
30
31define <2 x i1> @vtrunc_v2i1_v2i32(<2 x i32> %a, <2 x i1> %m, i32 zeroext %vl) {
32; CHECK-LABEL: vtrunc_v2i1_v2i32:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
35; CHECK-NEXT:    vand.vi v8, v8, 1, v0.t
36; CHECK-NEXT:    vmsne.vi v0, v8, 0, v0.t
37; CHECK-NEXT:    ret
38  %v = call <2 x i1> @llvm.vp.trunc.v2i1.v2i32(<2 x i32> %a, <2 x i1> %m, i32 %vl)
39  ret <2 x i1> %v
40}
41
42define <2 x i1> @vtrunc_v2i1_v2i32_unmasked(<2 x i32> %a, i32 zeroext %vl) {
43; CHECK-LABEL: vtrunc_v2i1_v2i32_unmasked:
44; CHECK:       # %bb.0:
45; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
46; CHECK-NEXT:    vand.vi v8, v8, 1
47; CHECK-NEXT:    vmsne.vi v0, v8, 0
48; CHECK-NEXT:    ret
49  %v = call <2 x i1> @llvm.vp.trunc.v2i1.v2i32(<2 x i32> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)
50  ret <2 x i1> %v
51}
52
53declare <2 x i1> @llvm.vp.trunc.v2i1.v2i64(<2 x i64>, <2 x i1>, i32)
54
55define <2 x i1> @vtrunc_v2i1_v2i64(<2 x i64> %a, <2 x i1> %m, i32 zeroext %vl) {
56; CHECK-LABEL: vtrunc_v2i1_v2i64:
57; CHECK:       # %bb.0:
58; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
59; CHECK-NEXT:    vand.vi v8, v8, 1, v0.t
60; CHECK-NEXT:    vmsne.vi v0, v8, 0, v0.t
61; CHECK-NEXT:    ret
62  %v = call <2 x i1> @llvm.vp.trunc.v2i1.v2i64(<2 x i64> %a, <2 x i1> %m, i32 %vl)
63  ret <2 x i1> %v
64}
65
66define <2 x i1> @vtrunc_v2i1_v2i64_unmasked(<2 x i64> %a, i32 zeroext %vl) {
67; CHECK-LABEL: vtrunc_v2i1_v2i64_unmasked:
68; CHECK:       # %bb.0:
69; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
70; CHECK-NEXT:    vand.vi v8, v8, 1
71; CHECK-NEXT:    vmsne.vi v0, v8, 0
72; CHECK-NEXT:    ret
73  %v = call <2 x i1> @llvm.vp.trunc.v2i1.v2i64(<2 x i64> %a, <2 x i1> <i1 true, i1 true>, i32 %vl)
74  ret <2 x i1> %v
75}
76