xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll (revision 1cb599835ccf7ee8b2d1d5a7f3107e19a26fc6f5) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh < %s | FileCheck %s
3; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh < %s | FileCheck %s
4
5declare <4 x half> @llvm.vp.sitofp.v4f16.v4i1(<4 x i1>, <4 x i1>, i32)
6
7define <4 x half> @vsitofp_v4f16_v4i1(<4 x i1> %va, <4 x i1> %m, i32 zeroext %evl) {
8; CHECK-LABEL: vsitofp_v4f16_v4i1:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
11; CHECK-NEXT:    vmv.v.i v9, 0
12; CHECK-NEXT:    vmerge.vim v9, v9, -1, v0
13; CHECK-NEXT:    vmv1r.v v0, v8
14; CHECK-NEXT:    vfcvt.f.x.v v8, v9, v0.t
15; CHECK-NEXT:    ret
16  %v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i1(<4 x i1> %va, <4 x i1> %m, i32 %evl)
17  ret <4 x half> %v
18}
19
20define <4 x half> @vsitofp_v4f16_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) {
21; CHECK-LABEL: vsitofp_v4f16_v4i1_unmasked:
22; CHECK:       # %bb.0:
23; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
24; CHECK-NEXT:    vmv.v.i v8, 0
25; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
26; CHECK-NEXT:    vfcvt.f.x.v v8, v8
27; CHECK-NEXT:    ret
28  %v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i1(<4 x i1> %va, <4 x i1> splat (i1 true), i32 %evl)
29  ret <4 x half> %v
30}
31
32declare <4 x float> @llvm.vp.sitofp.v4f32.v4i1(<4 x i1>, <4 x i1>, i32)
33
34define <4 x float> @vsitofp_v4f32_v4i1(<4 x i1> %va, <4 x i1> %m, i32 zeroext %evl) {
35; CHECK-LABEL: vsitofp_v4f32_v4i1:
36; CHECK:       # %bb.0:
37; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
38; CHECK-NEXT:    vmv.v.i v9, 0
39; CHECK-NEXT:    vmerge.vim v9, v9, -1, v0
40; CHECK-NEXT:    vmv1r.v v0, v8
41; CHECK-NEXT:    vfcvt.f.x.v v8, v9, v0.t
42; CHECK-NEXT:    ret
43  %v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i1(<4 x i1> %va, <4 x i1> %m, i32 %evl)
44  ret <4 x float> %v
45}
46
47define <4 x float> @vsitofp_v4f32_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) {
48; CHECK-LABEL: vsitofp_v4f32_v4i1_unmasked:
49; CHECK:       # %bb.0:
50; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
51; CHECK-NEXT:    vmv.v.i v8, 0
52; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
53; CHECK-NEXT:    vfcvt.f.x.v v8, v8
54; CHECK-NEXT:    ret
55  %v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i1(<4 x i1> %va, <4 x i1> splat (i1 true), i32 %evl)
56  ret <4 x float> %v
57}
58
59declare <4 x double> @llvm.vp.sitofp.v4f64.v4i1(<4 x i1>, <4 x i1>, i32)
60
61define <4 x double> @vsitofp_v4f64_v4i1(<4 x i1> %va, <4 x i1> %m, i32 zeroext %evl) {
62; CHECK-LABEL: vsitofp_v4f64_v4i1:
63; CHECK:       # %bb.0:
64; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
65; CHECK-NEXT:    vmv.v.i v10, 0
66; CHECK-NEXT:    vmerge.vim v10, v10, -1, v0
67; CHECK-NEXT:    vmv1r.v v0, v8
68; CHECK-NEXT:    vfcvt.f.x.v v8, v10, v0.t
69; CHECK-NEXT:    ret
70  %v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i1(<4 x i1> %va, <4 x i1> %m, i32 %evl)
71  ret <4 x double> %v
72}
73
74define <4 x double> @vsitofp_v4f64_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) {
75; CHECK-LABEL: vsitofp_v4f64_v4i1_unmasked:
76; CHECK:       # %bb.0:
77; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
78; CHECK-NEXT:    vmv.v.i v8, 0
79; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
80; CHECK-NEXT:    vfcvt.f.x.v v8, v8
81; CHECK-NEXT:    ret
82  %v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i1(<4 x i1> %va, <4 x i1> splat (i1 true), i32 %evl)
83  ret <4 x double> %v
84}
85