xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-segN-store.ll (revision 37b474a20e8a731bec9db7033e02013c07bd6fa4) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs | FileCheck %s
3; RUN: sed 's/iXLen/i64/g' %s |llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s
4
5declare void @llvm.riscv.seg2.store.v8i8.p0.iXLen(<8 x i8>, <8 x i8>, ptr, iXLen)
6define void @store_factor2(<8 x i8> %v0, <8 x i8> %v1, ptr %ptr) {
7; CHECK-LABEL: store_factor2:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
10; CHECK-NEXT:    vsseg2e8.v v8, (a0)
11; CHECK-NEXT:    ret
12    call void @llvm.riscv.seg2.store.v8i8.p0.iXLen(<8 x i8> %v0, <8 x i8> %v1, ptr %ptr, iXLen 8)
13    ret void
14}
15
16declare void @llvm.riscv.seg3.store.v8i8.p0.iXLen(<8 x i8>, <8 x i8>, <8 x i8>, ptr, iXLen)
17define void @store_factor3(<8 x i8> %v0, <8 x i8> %v1, <8 x i8> %v2, ptr %ptr) {
18; CHECK-LABEL: store_factor3:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
21; CHECK-NEXT:    vsseg3e8.v v8, (a0)
22; CHECK-NEXT:    ret
23    call void @llvm.riscv.seg3.store.v8i8.p0.iXLen(<8 x i8> %v0, <8 x i8> %v1, <8 x i8> %v2, ptr %ptr, iXLen 8)
24    ret void
25}
26
27declare void @llvm.riscv.seg4.store.v8i8.p0.iXLen(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, ptr, iXLen)
28define void @store_factor4(<8 x i8> %v0, <8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3, ptr %ptr) {
29; CHECK-LABEL: store_factor4:
30; CHECK:       # %bb.0:
31; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
32; CHECK-NEXT:    vsseg4e8.v v8, (a0)
33; CHECK-NEXT:    ret
34    call void @llvm.riscv.seg4.store.v8i8.p0.iXLen(<8 x i8> %v0, <8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3, ptr %ptr, iXLen 8)
35    ret void
36}
37
38declare void @llvm.riscv.seg5.store.v8i8.p0.iXLen(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, ptr, iXLen)
39define void @store_factor5(<8 x i8> %v0, <8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3, <8 x i8> %v4, ptr %ptr) {
40; CHECK-LABEL: store_factor5:
41; CHECK:       # %bb.0:
42; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
43; CHECK-NEXT:    vsseg5e8.v v8, (a0)
44; CHECK-NEXT:    ret
45    call void @llvm.riscv.seg5.store.v8i8.p0.iXLen(<8 x i8> %v0, <8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3, <8 x i8> %v4, ptr %ptr, iXLen 8)
46    ret void
47}
48
49declare void @llvm.riscv.seg6.store.v8i8.p0.iXLen(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, ptr, iXLen)
50define void @store_factor6(<8 x i8> %v0, <8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3, <8 x i8> %v4, <8 x i8> %v5, ptr %ptr) {
51; CHECK-LABEL: store_factor6:
52; CHECK:       # %bb.0:
53; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
54; CHECK-NEXT:    vsseg6e8.v v8, (a0)
55; CHECK-NEXT:    ret
56    call void @llvm.riscv.seg6.store.v8i8.p0.iXLen(<8 x i8> %v0, <8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3, <8 x i8> %v4, <8 x i8> %v5, ptr %ptr, iXLen 8)
57    ret void
58}
59
60declare void @llvm.riscv.seg7.store.v8i8.p0.iXLen(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8x i8>, ptr, iXLen)
61define void @store_factor7(<8 x i8> %v0, <8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3, <8 x i8> %v4, <8 x i8> %v5, <8 x i8> %v6, ptr %ptr) {
62; CHECK-LABEL: store_factor7:
63; CHECK:       # %bb.0:
64; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
65; CHECK-NEXT:    vsseg7e8.v v8, (a0)
66; CHECK-NEXT:    ret
67    call void @llvm.riscv.seg7.store.v8i8.p0.iXLen(<8 x i8> %v0, <8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3, <8 x i8> %v4, <8 x i8> %v5, <8 x i8> %v6, ptr %ptr, iXLen 8)
68    ret void
69}
70
71declare void @llvm.riscv.seg8.store.v8i8.p0.iXLen(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, ptr, iXLen)
72define void @store_factor8(<8 x i8> %v0, <8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3, <8 x i8> %v4, <8 x i8> %v5, <8 x i8> %v6, <8 x i8> %v7, ptr %ptr) {
73; CHECK-LABEL: store_factor8:
74; CHECK:       # %bb.0:
75; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
76; CHECK-NEXT:    vsseg8e8.v v8, (a0)
77; CHECK-NEXT:    ret
78    call void @llvm.riscv.seg8.store.v8i8.p0.iXLen(<8 x i8> %v0, <8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3, <8 x i8> %v4, <8 x i8> %v5, <8 x i8> %v6, <8 x i8> %v7, ptr %ptr, iXLen 8)
79    ret void
80}
81