xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-segN-load.ll (revision 74f985b793bf4005e49736f8c2cef8b5cbf7c1ab) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple riscv64 -mattr=+zve64x,+zvl128b < %s | FileCheck %s
3
4define <8 x i8> @load_factor2(ptr %ptr) {
5; CHECK-LABEL: load_factor2:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
8; CHECK-NEXT:    vlseg2e8.v v7, (a0)
9; CHECK-NEXT:    ret
10    %1 = call { <8 x i8>, <8 x i8> } @llvm.riscv.seg2.load.v8i8.p0.i64(ptr %ptr, i64 8)
11    %2 = extractvalue { <8 x i8>, <8 x i8> } %1, 0
12    %3 = extractvalue { <8 x i8>, <8 x i8> } %1, 1
13    ret <8 x i8> %3
14}
15
16define <8 x i8> @load_factor3(ptr %ptr) {
17; CHECK-LABEL: load_factor3:
18; CHECK:       # %bb.0:
19; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
20; CHECK-NEXT:    vlseg3e8.v v6, (a0)
21; CHECK-NEXT:    ret
22    %1 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg3.load.v8i8.p0.i64(ptr %ptr, i64 8)
23    %2 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %1, 0
24    %3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %1, 1
25    %4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %1, 2
26    ret <8 x i8> %4
27}
28
29define <8 x i8> @load_factor4(ptr %ptr) {
30; CHECK-LABEL: load_factor4:
31; CHECK:       # %bb.0:
32; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
33; CHECK-NEXT:    vlseg4e8.v v5, (a0)
34; CHECK-NEXT:    ret
35    %1 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg4.load.v8i8.p0.i64(ptr %ptr, i64 8)
36    %2 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 0
37    %3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 1
38    %4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 2
39    %5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 3
40    ret <8 x i8> %5
41}
42
43define <8 x i8> @load_factor5(ptr %ptr) {
44; CHECK-LABEL: load_factor5:
45; CHECK:       # %bb.0:
46; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
47; CHECK-NEXT:    vlseg5e8.v v4, (a0)
48; CHECK-NEXT:    ret
49    %1 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg5.load.v8i8.p0.i64(ptr %ptr, i64 8)
50    %2 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 0
51    %3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 1
52    %4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 2
53    %5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 3
54    %6 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 4
55    ret <8 x i8> %6
56}
57
58define <8 x i8> @load_factor6(ptr %ptr) {
59; CHECK-LABEL: load_factor6:
60; CHECK:       # %bb.0:
61; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
62; CHECK-NEXT:    vlseg6e8.v v3, (a0)
63; CHECK-NEXT:    ret
64    %1 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg6.load.v8i8.p0.i64(ptr %ptr, i64 8)
65    %2 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 0
66    %3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 1
67    %4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 2
68    %5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 3
69    %6 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 4
70    %7 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 5
71    ret <8 x i8> %7
72}
73
74define <8 x i8> @load_factor7(ptr %ptr) {
75; CHECK-LABEL: load_factor7:
76; CHECK:       # %bb.0:
77; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
78; CHECK-NEXT:    vlseg7e8.v v2, (a0)
79; CHECK-NEXT:    ret
80    %1 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg7.load.v8i8.p0.i64(ptr %ptr, i64 8)
81    %2 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 0
82    %3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 1
83    %4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 2
84    %5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 3
85    %6 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 4
86    %7 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 5
87    %8 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 6
88    ret <8 x i8> %8
89}
90
91define <8 x i8> @load_factor8(ptr %ptr) {
92; CHECK-LABEL: load_factor8:
93; CHECK:       # %bb.0:
94; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
95; CHECK-NEXT:    vlseg8e8.v v1, (a0)
96; CHECK-NEXT:    ret
97    %1 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg8.load.v8i8.p0.i64(ptr %ptr, i64 8)
98    %2 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 0
99    %3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 1
100    %4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 2
101    %5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 3
102    %6 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 4
103    %7 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 5
104    %8 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 6
105    %9 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 7
106    ret <8 x i8> %9
107}
108declare { <8 x i8>, <8 x i8> } @llvm.riscv.seg2.load.v8i8.p0.i64(ptr, i64)
109declare { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg3.load.v8i8.p0.i64(ptr, i64)
110declare { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg4.load.v8i8.p0.i64(ptr, i64)
111declare { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg5.load.v8i8.p0.i64(ptr, i64)
112declare { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg6.load.v8i8.p0.i64(ptr, i64)
113declare { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg7.load.v8i8.p0.i64(ptr, i64)
114declare { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg8.load.v8i8.p0.i64(ptr, i64)
115