xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll (revision afc7cc7b123666a8917b26c7e483d78cbb79ff8d) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+f,+d \
3; RUN:     -target-abi=ilp32d -verify-machineinstrs | FileCheck %s --check-prefix=RV32
4; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv64 -mattr=+v,+f,+d \
5; RUN:     -target-abi=lp64d -verify-machineinstrs | FileCheck %s --check-prefix=RV64-i32
6; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+f,+d \
7; RUN:     -target-abi=lp64d -verify-machineinstrs | FileCheck %s --check-prefix=RV64-i64
8
9define <1 x iXLen> @lrint_v1f32(<1 x float> %x, <1 x i1> %m, i32 zeroext %evl) {
10; RV32-LABEL: lrint_v1f32:
11; RV32:       # %bb.0:
12; RV32-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
13; RV32-NEXT:    vfcvt.x.f.v v8, v8, v0.t
14; RV32-NEXT:    ret
15;
16; RV64-i32-LABEL: lrint_v1f32:
17; RV64-i32:       # %bb.0:
18; RV64-i32-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
19; RV64-i32-NEXT:    vfcvt.x.f.v v8, v8, v0.t
20; RV64-i32-NEXT:    ret
21;
22; RV64-i64-LABEL: lrint_v1f32:
23; RV64-i64:       # %bb.0:
24; RV64-i64-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
25; RV64-i64-NEXT:    vfwcvt.x.f.v v9, v8, v0.t
26; RV64-i64-NEXT:    vmv1r.v v8, v9
27; RV64-i64-NEXT:    ret
28  %a = call <1 x iXLen> @llvm.vp.lrint.v1iXLen.v1f32(<1 x float> %x, <1 x i1> %m, i32 %evl)
29  ret <1 x iXLen> %a
30}
31declare <1 x iXLen> @llvm.vp.lrint.v1iXLen.v1f32(<1 x float>, <1 x i1>, i32)
32
33define <2 x iXLen> @lrint_v2f32(<2 x float> %x, <2 x i1> %m, i32 zeroext %evl) {
34; RV32-LABEL: lrint_v2f32:
35; RV32:       # %bb.0:
36; RV32-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
37; RV32-NEXT:    vfcvt.x.f.v v8, v8, v0.t
38; RV32-NEXT:    ret
39;
40; RV64-i32-LABEL: lrint_v2f32:
41; RV64-i32:       # %bb.0:
42; RV64-i32-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
43; RV64-i32-NEXT:    vfcvt.x.f.v v8, v8, v0.t
44; RV64-i32-NEXT:    ret
45;
46; RV64-i64-LABEL: lrint_v2f32:
47; RV64-i64:       # %bb.0:
48; RV64-i64-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
49; RV64-i64-NEXT:    vfwcvt.x.f.v v9, v8, v0.t
50; RV64-i64-NEXT:    vmv1r.v v8, v9
51; RV64-i64-NEXT:    ret
52  %a = call <2 x iXLen> @llvm.vp.lrint.v2iXLen.v2f32(<2 x float> %x, <2 x i1> %m, i32 %evl)
53  ret <2 x iXLen> %a
54}
55declare <2 x iXLen> @llvm.vp.lrint.v2iXLen.v2f32(<2 x float>, <2 x i1>, i32)
56
57define <3 x iXLen> @lrint_v3f32(<3 x float> %x, <3 x i1> %m, i32 zeroext %evl) {
58; RV32-LABEL: lrint_v3f32:
59; RV32:       # %bb.0:
60; RV32-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
61; RV32-NEXT:    vfcvt.x.f.v v8, v8, v0.t
62; RV32-NEXT:    ret
63;
64; RV64-i32-LABEL: lrint_v3f32:
65; RV64-i32:       # %bb.0:
66; RV64-i32-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
67; RV64-i32-NEXT:    vfcvt.x.f.v v8, v8, v0.t
68; RV64-i32-NEXT:    ret
69;
70; RV64-i64-LABEL: lrint_v3f32:
71; RV64-i64:       # %bb.0:
72; RV64-i64-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
73; RV64-i64-NEXT:    vfwcvt.x.f.v v10, v8, v0.t
74; RV64-i64-NEXT:    vmv2r.v v8, v10
75; RV64-i64-NEXT:    ret
76  %a = call <3 x iXLen> @llvm.vp.lrint.v3iXLen.v3f32(<3 x float> %x, <3 x i1> %m, i32 %evl)
77  ret <3 x iXLen> %a
78}
79declare <3 x iXLen> @llvm.vp.lrint.v3iXLen.v3f32(<3 x float>, <3 x i1>, i32)
80
81define <4 x iXLen> @lrint_v4f32(<4 x float> %x, <4 x i1> %m, i32 zeroext %evl) {
82; RV32-LABEL: lrint_v4f32:
83; RV32:       # %bb.0:
84; RV32-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
85; RV32-NEXT:    vfcvt.x.f.v v8, v8, v0.t
86; RV32-NEXT:    ret
87;
88; RV64-i32-LABEL: lrint_v4f32:
89; RV64-i32:       # %bb.0:
90; RV64-i32-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
91; RV64-i32-NEXT:    vfcvt.x.f.v v8, v8, v0.t
92; RV64-i32-NEXT:    ret
93;
94; RV64-i64-LABEL: lrint_v4f32:
95; RV64-i64:       # %bb.0:
96; RV64-i64-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
97; RV64-i64-NEXT:    vfwcvt.x.f.v v10, v8, v0.t
98; RV64-i64-NEXT:    vmv2r.v v8, v10
99; RV64-i64-NEXT:    ret
100  %a = call <4 x iXLen> @llvm.vp.lrint.v4iXLen.v4f32(<4 x float> %x, <4 x i1> %m, i32 %evl)
101  ret <4 x iXLen> %a
102}
103declare <4 x iXLen> @llvm.vp.lrint.v4iXLen.v4f32(<4 x float>, <4 x i1>, i32)
104
105define <8 x iXLen> @lrint_v8f32(<8 x float> %x, <8 x i1> %m, i32 zeroext %evl) {
106; RV32-LABEL: lrint_v8f32:
107; RV32:       # %bb.0:
108; RV32-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
109; RV32-NEXT:    vfcvt.x.f.v v8, v8, v0.t
110; RV32-NEXT:    ret
111;
112; RV64-i32-LABEL: lrint_v8f32:
113; RV64-i32:       # %bb.0:
114; RV64-i32-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
115; RV64-i32-NEXT:    vfcvt.x.f.v v8, v8, v0.t
116; RV64-i32-NEXT:    ret
117;
118; RV64-i64-LABEL: lrint_v8f32:
119; RV64-i64:       # %bb.0:
120; RV64-i64-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
121; RV64-i64-NEXT:    vfwcvt.x.f.v v12, v8, v0.t
122; RV64-i64-NEXT:    vmv4r.v v8, v12
123; RV64-i64-NEXT:    ret
124  %a = call <8 x iXLen> @llvm.vp.lrint.v8iXLen.v8f32(<8 x float> %x, <8 x i1> %m, i32 %evl)
125  ret <8 x iXLen> %a
126}
127declare <8 x iXLen> @llvm.vp.lrint.v8iXLen.v8f32(<8 x float>, <8 x i1>, i32)
128
129define <16 x iXLen> @lrint_v16f32(<16 x float> %x, <16 x i1> %m, i32 zeroext %evl) {
130; RV32-LABEL: lrint_v16f32:
131; RV32:       # %bb.0:
132; RV32-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
133; RV32-NEXT:    vfcvt.x.f.v v8, v8, v0.t
134; RV32-NEXT:    ret
135;
136; RV64-i32-LABEL: lrint_v16f32:
137; RV64-i32:       # %bb.0:
138; RV64-i32-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
139; RV64-i32-NEXT:    vfcvt.x.f.v v8, v8, v0.t
140; RV64-i32-NEXT:    ret
141;
142; RV64-i64-LABEL: lrint_v16f32:
143; RV64-i64:       # %bb.0:
144; RV64-i64-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
145; RV64-i64-NEXT:    vfwcvt.x.f.v v16, v8, v0.t
146; RV64-i64-NEXT:    vmv8r.v v8, v16
147; RV64-i64-NEXT:    ret
148  %a = call <16 x iXLen> @llvm.vp.lrint.v16iXLen.v16f32(<16 x float> %x, <16 x i1> %m, i32 %evl)
149  ret <16 x iXLen> %a
150}
151declare <16 x iXLen> @llvm.vp.lrint.v16iXLen.v16f32(<16 x float>, <16 x i1>, i32)
152
153define <1 x iXLen> @lrint_v1f64(<1 x double> %x, <1 x i1> %m, i32 zeroext %evl) {
154; RV32-LABEL: lrint_v1f64:
155; RV32:       # %bb.0:
156; RV32-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
157; RV32-NEXT:    vfncvt.x.f.w v9, v8, v0.t
158; RV32-NEXT:    vmv1r.v v8, v9
159; RV32-NEXT:    ret
160;
161; RV64-i32-LABEL: lrint_v1f64:
162; RV64-i32:       # %bb.0:
163; RV64-i32-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
164; RV64-i32-NEXT:    vfncvt.x.f.w v9, v8, v0.t
165; RV64-i32-NEXT:    vmv1r.v v8, v9
166; RV64-i32-NEXT:    ret
167;
168; RV64-i64-LABEL: lrint_v1f64:
169; RV64-i64:       # %bb.0:
170; RV64-i64-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
171; RV64-i64-NEXT:    vfcvt.x.f.v v8, v8, v0.t
172; RV64-i64-NEXT:    ret
173  %a = call <1 x iXLen> @llvm.vp.lrint.v1iXLen.v1f64(<1 x double> %x, <1 x i1> %m, i32 %evl)
174  ret <1 x iXLen> %a
175}
176declare <1 x iXLen> @llvm.vp.lrint.v1iXLen.v1f64(<1 x double>, <1 x i1>, i32)
177
178define <2 x iXLen> @lrint_v2f64(<2 x double> %x, <2 x i1> %m, i32 zeroext %evl) {
179; RV32-LABEL: lrint_v2f64:
180; RV32:       # %bb.0:
181; RV32-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
182; RV32-NEXT:    vfncvt.x.f.w v9, v8, v0.t
183; RV32-NEXT:    vmv1r.v v8, v9
184; RV32-NEXT:    ret
185;
186; RV64-i32-LABEL: lrint_v2f64:
187; RV64-i32:       # %bb.0:
188; RV64-i32-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
189; RV64-i32-NEXT:    vfncvt.x.f.w v9, v8, v0.t
190; RV64-i32-NEXT:    vmv1r.v v8, v9
191; RV64-i32-NEXT:    ret
192;
193; RV64-i64-LABEL: lrint_v2f64:
194; RV64-i64:       # %bb.0:
195; RV64-i64-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
196; RV64-i64-NEXT:    vfcvt.x.f.v v8, v8, v0.t
197; RV64-i64-NEXT:    ret
198  %a = call <2 x iXLen> @llvm.vp.lrint.v2iXLen.v2f64(<2 x double> %x, <2 x i1> %m, i32 %evl)
199  ret <2 x iXLen> %a
200}
201declare <2 x iXLen> @llvm.vp.lrint.v2iXLen.v2f64(<2 x double>, <2 x i1>, i32)
202
203define <4 x iXLen> @lrint_v4f64(<4 x double> %x, <4 x i1> %m, i32 zeroext %evl) {
204; RV32-LABEL: lrint_v4f64:
205; RV32:       # %bb.0:
206; RV32-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
207; RV32-NEXT:    vfncvt.x.f.w v10, v8, v0.t
208; RV32-NEXT:    vmv.v.v v8, v10
209; RV32-NEXT:    ret
210;
211; RV64-i32-LABEL: lrint_v4f64:
212; RV64-i32:       # %bb.0:
213; RV64-i32-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
214; RV64-i32-NEXT:    vfncvt.x.f.w v10, v8, v0.t
215; RV64-i32-NEXT:    vmv.v.v v8, v10
216; RV64-i32-NEXT:    ret
217;
218; RV64-i64-LABEL: lrint_v4f64:
219; RV64-i64:       # %bb.0:
220; RV64-i64-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
221; RV64-i64-NEXT:    vfcvt.x.f.v v8, v8, v0.t
222; RV64-i64-NEXT:    ret
223  %a = call <4 x iXLen> @llvm.vp.lrint.v4iXLen.v4f64(<4 x double> %x, <4 x i1> %m, i32 %evl)
224  ret <4 x iXLen> %a
225}
226declare <4 x iXLen> @llvm.vp.lrint.v4iXLen.v4f64(<4 x double>, <4 x i1>, i32)
227
228define <8 x iXLen> @lrint_v8f64(<8 x double> %x, <8 x i1> %m, i32 zeroext %evl) {
229; RV32-LABEL: lrint_v8f64:
230; RV32:       # %bb.0:
231; RV32-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
232; RV32-NEXT:    vfncvt.x.f.w v12, v8, v0.t
233; RV32-NEXT:    vmv.v.v v8, v12
234; RV32-NEXT:    ret
235;
236; RV64-i32-LABEL: lrint_v8f64:
237; RV64-i32:       # %bb.0:
238; RV64-i32-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
239; RV64-i32-NEXT:    vfncvt.x.f.w v12, v8, v0.t
240; RV64-i32-NEXT:    vmv.v.v v8, v12
241; RV64-i32-NEXT:    ret
242;
243; RV64-i64-LABEL: lrint_v8f64:
244; RV64-i64:       # %bb.0:
245; RV64-i64-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
246; RV64-i64-NEXT:    vfcvt.x.f.v v8, v8, v0.t
247; RV64-i64-NEXT:    ret
248  %a = call <8 x iXLen> @llvm.vp.lrint.v8iXLen.v8f64(<8 x double> %x, <8 x i1> %m, i32 %evl)
249  ret <8 x iXLen> %a
250}
251declare <8 x iXLen> @llvm.vp.lrint.v8iXLen.v8f64(<8 x double>, <8 x i1>, i32)
252