xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll (revision 1cb599835ccf7ee8b2d1d5a7f3107e19a26fc6f5) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
3; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
4; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
5; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
6
7declare <4 x i7> @llvm.vp.fptoui.v4i7.v4f16(<4 x half>, <4 x i1>, i32)
8
9define <4 x i7> @vfptoui_v4i7_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) {
10; ZVFH-LABEL: vfptoui_v4i7_v4f16:
11; ZVFH:       # %bb.0:
12; ZVFH-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
13; ZVFH-NEXT:    vfncvt.rtz.x.f.w v9, v8, v0.t
14; ZVFH-NEXT:    vmv1r.v v8, v9
15; ZVFH-NEXT:    ret
16;
17; ZVFHMIN-LABEL: vfptoui_v4i7_v4f16:
18; ZVFHMIN:       # %bb.0:
19; ZVFHMIN-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
20; ZVFHMIN-NEXT:    vfwcvt.f.f.v v9, v8
21; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
22; ZVFHMIN-NEXT:    vfncvt.rtz.x.f.w v8, v9, v0.t
23; ZVFHMIN-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
24; ZVFHMIN-NEXT:    vnsrl.wi v8, v8, 0, v0.t
25; ZVFHMIN-NEXT:    ret
26  %v = call <4 x i7> @llvm.vp.fptoui.v4i7.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl)
27  ret <4 x i7> %v
28}
29
30declare <4 x i8> @llvm.vp.fptoui.v4i8.v4f16(<4 x half>, <4 x i1>, i32)
31
32define <4 x i8> @vfptoui_v4i8_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) {
33; ZVFH-LABEL: vfptoui_v4i8_v4f16:
34; ZVFH:       # %bb.0:
35; ZVFH-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
36; ZVFH-NEXT:    vfncvt.rtz.xu.f.w v9, v8, v0.t
37; ZVFH-NEXT:    vmv1r.v v8, v9
38; ZVFH-NEXT:    ret
39;
40; ZVFHMIN-LABEL: vfptoui_v4i8_v4f16:
41; ZVFHMIN:       # %bb.0:
42; ZVFHMIN-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
43; ZVFHMIN-NEXT:    vfwcvt.f.f.v v9, v8
44; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
45; ZVFHMIN-NEXT:    vfncvt.rtz.xu.f.w v8, v9, v0.t
46; ZVFHMIN-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
47; ZVFHMIN-NEXT:    vnsrl.wi v8, v8, 0, v0.t
48; ZVFHMIN-NEXT:    ret
49  %v = call <4 x i8> @llvm.vp.fptoui.v4i8.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl)
50  ret <4 x i8> %v
51}
52
53define <4 x i8> @vfptoui_v4i8_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) {
54; ZVFH-LABEL: vfptoui_v4i8_v4f16_unmasked:
55; ZVFH:       # %bb.0:
56; ZVFH-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
57; ZVFH-NEXT:    vfncvt.rtz.xu.f.w v9, v8
58; ZVFH-NEXT:    vmv1r.v v8, v9
59; ZVFH-NEXT:    ret
60;
61; ZVFHMIN-LABEL: vfptoui_v4i8_v4f16_unmasked:
62; ZVFHMIN:       # %bb.0:
63; ZVFHMIN-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
64; ZVFHMIN-NEXT:    vfwcvt.f.f.v v9, v8
65; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
66; ZVFHMIN-NEXT:    vfncvt.rtz.xu.f.w v8, v9
67; ZVFHMIN-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
68; ZVFHMIN-NEXT:    vnsrl.wi v8, v8, 0
69; ZVFHMIN-NEXT:    ret
70  %v = call <4 x i8> @llvm.vp.fptoui.v4i8.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl)
71  ret <4 x i8> %v
72}
73
74declare <4 x i16> @llvm.vp.fptoui.v4i16.v4f16(<4 x half>, <4 x i1>, i32)
75
76define <4 x i16> @vfptoui_v4i16_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) {
77; ZVFH-LABEL: vfptoui_v4i16_v4f16:
78; ZVFH:       # %bb.0:
79; ZVFH-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
80; ZVFH-NEXT:    vfcvt.rtz.xu.f.v v8, v8, v0.t
81; ZVFH-NEXT:    ret
82;
83; ZVFHMIN-LABEL: vfptoui_v4i16_v4f16:
84; ZVFHMIN:       # %bb.0:
85; ZVFHMIN-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
86; ZVFHMIN-NEXT:    vfwcvt.f.f.v v9, v8
87; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
88; ZVFHMIN-NEXT:    vfncvt.rtz.xu.f.w v8, v9, v0.t
89; ZVFHMIN-NEXT:    ret
90  %v = call <4 x i16> @llvm.vp.fptoui.v4i16.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl)
91  ret <4 x i16> %v
92}
93
94define <4 x i16> @vfptoui_v4i16_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) {
95; ZVFH-LABEL: vfptoui_v4i16_v4f16_unmasked:
96; ZVFH:       # %bb.0:
97; ZVFH-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
98; ZVFH-NEXT:    vfcvt.rtz.xu.f.v v8, v8
99; ZVFH-NEXT:    ret
100;
101; ZVFHMIN-LABEL: vfptoui_v4i16_v4f16_unmasked:
102; ZVFHMIN:       # %bb.0:
103; ZVFHMIN-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
104; ZVFHMIN-NEXT:    vfwcvt.f.f.v v9, v8
105; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
106; ZVFHMIN-NEXT:    vfncvt.rtz.xu.f.w v8, v9
107; ZVFHMIN-NEXT:    ret
108  %v = call <4 x i16> @llvm.vp.fptoui.v4i16.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl)
109  ret <4 x i16> %v
110}
111
112declare <4 x i32> @llvm.vp.fptoui.v4i32.v4f16(<4 x half>, <4 x i1>, i32)
113
114define <4 x i32> @vfptoui_v4i32_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) {
115; ZVFH-LABEL: vfptoui_v4i32_v4f16:
116; ZVFH:       # %bb.0:
117; ZVFH-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
118; ZVFH-NEXT:    vfwcvt.rtz.xu.f.v v9, v8, v0.t
119; ZVFH-NEXT:    vmv1r.v v8, v9
120; ZVFH-NEXT:    ret
121;
122; ZVFHMIN-LABEL: vfptoui_v4i32_v4f16:
123; ZVFHMIN:       # %bb.0:
124; ZVFHMIN-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
125; ZVFHMIN-NEXT:    vfwcvt.f.f.v v9, v8
126; ZVFHMIN-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
127; ZVFHMIN-NEXT:    vfcvt.rtz.xu.f.v v8, v9, v0.t
128; ZVFHMIN-NEXT:    ret
129  %v = call <4 x i32> @llvm.vp.fptoui.v4i32.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl)
130  ret <4 x i32> %v
131}
132
133define <4 x i32> @vfptoui_v4i32_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) {
134; ZVFH-LABEL: vfptoui_v4i32_v4f16_unmasked:
135; ZVFH:       # %bb.0:
136; ZVFH-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
137; ZVFH-NEXT:    vfwcvt.rtz.xu.f.v v9, v8
138; ZVFH-NEXT:    vmv1r.v v8, v9
139; ZVFH-NEXT:    ret
140;
141; ZVFHMIN-LABEL: vfptoui_v4i32_v4f16_unmasked:
142; ZVFHMIN:       # %bb.0:
143; ZVFHMIN-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
144; ZVFHMIN-NEXT:    vfwcvt.f.f.v v9, v8
145; ZVFHMIN-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
146; ZVFHMIN-NEXT:    vfcvt.rtz.xu.f.v v8, v9
147; ZVFHMIN-NEXT:    ret
148  %v = call <4 x i32> @llvm.vp.fptoui.v4i32.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl)
149  ret <4 x i32> %v
150}
151
152declare <4 x i64> @llvm.vp.fptoui.v4i64.v4f16(<4 x half>, <4 x i1>, i32)
153
154define <4 x i64> @vfptoui_v4i64_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) {
155; ZVFH-LABEL: vfptoui_v4i64_v4f16:
156; ZVFH:       # %bb.0:
157; ZVFH-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
158; ZVFH-NEXT:    vfwcvt.f.f.v v10, v8, v0.t
159; ZVFH-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
160; ZVFH-NEXT:    vfwcvt.rtz.xu.f.v v8, v10, v0.t
161; ZVFH-NEXT:    ret
162;
163; ZVFHMIN-LABEL: vfptoui_v4i64_v4f16:
164; ZVFHMIN:       # %bb.0:
165; ZVFHMIN-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
166; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8
167; ZVFHMIN-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
168; ZVFHMIN-NEXT:    vfwcvt.rtz.xu.f.v v8, v10, v0.t
169; ZVFHMIN-NEXT:    ret
170  %v = call <4 x i64> @llvm.vp.fptoui.v4i64.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl)
171  ret <4 x i64> %v
172}
173
174define <4 x i64> @vfptoui_v4i64_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) {
175; ZVFH-LABEL: vfptoui_v4i64_v4f16_unmasked:
176; ZVFH:       # %bb.0:
177; ZVFH-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
178; ZVFH-NEXT:    vfwcvt.f.f.v v10, v8
179; ZVFH-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
180; ZVFH-NEXT:    vfwcvt.rtz.xu.f.v v8, v10
181; ZVFH-NEXT:    ret
182;
183; ZVFHMIN-LABEL: vfptoui_v4i64_v4f16_unmasked:
184; ZVFHMIN:       # %bb.0:
185; ZVFHMIN-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
186; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8
187; ZVFHMIN-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
188; ZVFHMIN-NEXT:    vfwcvt.rtz.xu.f.v v8, v10
189; ZVFHMIN-NEXT:    ret
190  %v = call <4 x i64> @llvm.vp.fptoui.v4i64.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl)
191  ret <4 x i64> %v
192}
193
194declare <4 x i8> @llvm.vp.fptoui.v4i8.v4f32(<4 x float>, <4 x i1>, i32)
195
196define <4 x i8> @vfptoui_v4i8_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %evl) {
197; CHECK-LABEL: vfptoui_v4i8_v4f32:
198; CHECK:       # %bb.0:
199; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
200; CHECK-NEXT:    vfncvt.rtz.xu.f.w v9, v8, v0.t
201; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
202; CHECK-NEXT:    vnsrl.wi v8, v9, 0, v0.t
203; CHECK-NEXT:    ret
204  %v = call <4 x i8> @llvm.vp.fptoui.v4i8.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl)
205  ret <4 x i8> %v
206}
207
208define <4 x i8> @vfptoui_v4i8_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) {
209; CHECK-LABEL: vfptoui_v4i8_v4f32_unmasked:
210; CHECK:       # %bb.0:
211; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
212; CHECK-NEXT:    vfncvt.rtz.xu.f.w v9, v8
213; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
214; CHECK-NEXT:    vnsrl.wi v8, v9, 0
215; CHECK-NEXT:    ret
216  %v = call <4 x i8> @llvm.vp.fptoui.v4i8.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl)
217  ret <4 x i8> %v
218}
219
220declare <4 x i16> @llvm.vp.fptoui.v4i16.v4f32(<4 x float>, <4 x i1>, i32)
221
222define <4 x i16> @vfptoui_v4i16_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %evl) {
223; CHECK-LABEL: vfptoui_v4i16_v4f32:
224; CHECK:       # %bb.0:
225; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
226; CHECK-NEXT:    vfncvt.rtz.xu.f.w v9, v8, v0.t
227; CHECK-NEXT:    vmv1r.v v8, v9
228; CHECK-NEXT:    ret
229  %v = call <4 x i16> @llvm.vp.fptoui.v4i16.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl)
230  ret <4 x i16> %v
231}
232
233define <4 x i16> @vfptoui_v4i16_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) {
234; CHECK-LABEL: vfptoui_v4i16_v4f32_unmasked:
235; CHECK:       # %bb.0:
236; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
237; CHECK-NEXT:    vfncvt.rtz.xu.f.w v9, v8
238; CHECK-NEXT:    vmv1r.v v8, v9
239; CHECK-NEXT:    ret
240  %v = call <4 x i16> @llvm.vp.fptoui.v4i16.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl)
241  ret <4 x i16> %v
242}
243
244declare <4 x i32> @llvm.vp.fptoui.v4i32.v4f32(<4 x float>, <4 x i1>, i32)
245
246define <4 x i32> @vfptoui_v4i32_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %evl) {
247; CHECK-LABEL: vfptoui_v4i32_v4f32:
248; CHECK:       # %bb.0:
249; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
250; CHECK-NEXT:    vfcvt.rtz.xu.f.v v8, v8, v0.t
251; CHECK-NEXT:    ret
252  %v = call <4 x i32> @llvm.vp.fptoui.v4i32.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl)
253  ret <4 x i32> %v
254}
255
256define <4 x i32> @vfptoui_v4i32_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) {
257; CHECK-LABEL: vfptoui_v4i32_v4f32_unmasked:
258; CHECK:       # %bb.0:
259; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
260; CHECK-NEXT:    vfcvt.rtz.xu.f.v v8, v8
261; CHECK-NEXT:    ret
262  %v = call <4 x i32> @llvm.vp.fptoui.v4i32.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl)
263  ret <4 x i32> %v
264}
265
266declare <4 x i64> @llvm.vp.fptoui.v4i64.v4f32(<4 x float>, <4 x i1>, i32)
267
268define <4 x i64> @vfptoui_v4i64_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %evl) {
269; CHECK-LABEL: vfptoui_v4i64_v4f32:
270; CHECK:       # %bb.0:
271; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
272; CHECK-NEXT:    vfwcvt.rtz.xu.f.v v10, v8, v0.t
273; CHECK-NEXT:    vmv2r.v v8, v10
274; CHECK-NEXT:    ret
275  %v = call <4 x i64> @llvm.vp.fptoui.v4i64.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl)
276  ret <4 x i64> %v
277}
278
279define <4 x i64> @vfptoui_v4i64_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) {
280; CHECK-LABEL: vfptoui_v4i64_v4f32_unmasked:
281; CHECK:       # %bb.0:
282; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
283; CHECK-NEXT:    vfwcvt.rtz.xu.f.v v10, v8
284; CHECK-NEXT:    vmv2r.v v8, v10
285; CHECK-NEXT:    ret
286  %v = call <4 x i64> @llvm.vp.fptoui.v4i64.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl)
287  ret <4 x i64> %v
288}
289
290declare <4 x i8> @llvm.vp.fptoui.v4i8.v4f64(<4 x double>, <4 x i1>, i32)
291
292define <4 x i8> @vfptoui_v4i8_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %evl) {
293; CHECK-LABEL: vfptoui_v4i8_v4f64:
294; CHECK:       # %bb.0:
295; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
296; CHECK-NEXT:    vfncvt.rtz.xu.f.w v10, v8, v0.t
297; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
298; CHECK-NEXT:    vnsrl.wi v8, v10, 0, v0.t
299; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
300; CHECK-NEXT:    vnsrl.wi v8, v8, 0, v0.t
301; CHECK-NEXT:    ret
302  %v = call <4 x i8> @llvm.vp.fptoui.v4i8.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl)
303  ret <4 x i8> %v
304}
305
306define <4 x i8> @vfptoui_v4i8_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) {
307; CHECK-LABEL: vfptoui_v4i8_v4f64_unmasked:
308; CHECK:       # %bb.0:
309; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
310; CHECK-NEXT:    vfncvt.rtz.xu.f.w v10, v8
311; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
312; CHECK-NEXT:    vnsrl.wi v8, v10, 0
313; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
314; CHECK-NEXT:    vnsrl.wi v8, v8, 0
315; CHECK-NEXT:    ret
316  %v = call <4 x i8> @llvm.vp.fptoui.v4i8.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl)
317  ret <4 x i8> %v
318}
319
320declare <4 x i16> @llvm.vp.fptoui.v4i16.v4f64(<4 x double>, <4 x i1>, i32)
321
322define <4 x i16> @vfptoui_v4i16_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %evl) {
323; CHECK-LABEL: vfptoui_v4i16_v4f64:
324; CHECK:       # %bb.0:
325; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
326; CHECK-NEXT:    vfncvt.rtz.xu.f.w v10, v8, v0.t
327; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
328; CHECK-NEXT:    vnsrl.wi v8, v10, 0, v0.t
329; CHECK-NEXT:    ret
330  %v = call <4 x i16> @llvm.vp.fptoui.v4i16.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl)
331  ret <4 x i16> %v
332}
333
334define <4 x i16> @vfptoui_v4i16_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) {
335; CHECK-LABEL: vfptoui_v4i16_v4f64_unmasked:
336; CHECK:       # %bb.0:
337; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
338; CHECK-NEXT:    vfncvt.rtz.xu.f.w v10, v8
339; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
340; CHECK-NEXT:    vnsrl.wi v8, v10, 0
341; CHECK-NEXT:    ret
342  %v = call <4 x i16> @llvm.vp.fptoui.v4i16.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl)
343  ret <4 x i16> %v
344}
345
346declare <4 x i32> @llvm.vp.fptoui.v4i32.v4f64(<4 x double>, <4 x i1>, i32)
347
348define <4 x i32> @vfptoui_v4i32_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %evl) {
349; CHECK-LABEL: vfptoui_v4i32_v4f64:
350; CHECK:       # %bb.0:
351; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
352; CHECK-NEXT:    vfncvt.rtz.xu.f.w v10, v8, v0.t
353; CHECK-NEXT:    vmv.v.v v8, v10
354; CHECK-NEXT:    ret
355  %v = call <4 x i32> @llvm.vp.fptoui.v4i32.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl)
356  ret <4 x i32> %v
357}
358
359define <4 x i32> @vfptoui_v4i32_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) {
360; CHECK-LABEL: vfptoui_v4i32_v4f64_unmasked:
361; CHECK:       # %bb.0:
362; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
363; CHECK-NEXT:    vfncvt.rtz.xu.f.w v10, v8
364; CHECK-NEXT:    vmv.v.v v8, v10
365; CHECK-NEXT:    ret
366  %v = call <4 x i32> @llvm.vp.fptoui.v4i32.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl)
367  ret <4 x i32> %v
368}
369
370declare <4 x i64> @llvm.vp.fptoui.v4i64.v4f64(<4 x double>, <4 x i1>, i32)
371
372define <4 x i64> @vfptoui_v4i64_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %evl) {
373; CHECK-LABEL: vfptoui_v4i64_v4f64:
374; CHECK:       # %bb.0:
375; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
376; CHECK-NEXT:    vfcvt.rtz.xu.f.v v8, v8, v0.t
377; CHECK-NEXT:    ret
378  %v = call <4 x i64> @llvm.vp.fptoui.v4i64.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl)
379  ret <4 x i64> %v
380}
381
382define <4 x i64> @vfptoui_v4i64_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) {
383; CHECK-LABEL: vfptoui_v4i64_v4f64_unmasked:
384; CHECK:       # %bb.0:
385; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
386; CHECK-NEXT:    vfcvt.rtz.xu.f.v v8, v8
387; CHECK-NEXT:    ret
388  %v = call <4 x i64> @llvm.vp.fptoui.v4i64.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl)
389  ret <4 x i64> %v
390}
391
392declare <32 x i64> @llvm.vp.fptoui.v32i64.v32f64(<32 x double>, <32 x i1>, i32)
393
394define <32 x i64> @vfptoui_v32i64_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) {
395; CHECK-LABEL: vfptoui_v32i64_v32f64:
396; CHECK:       # %bb.0:
397; CHECK-NEXT:    li a2, 16
398; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
399; CHECK-NEXT:    vslidedown.vi v24, v0, 2
400; CHECK-NEXT:    mv a1, a0
401; CHECK-NEXT:    bltu a0, a2, .LBB25_2
402; CHECK-NEXT:  # %bb.1:
403; CHECK-NEXT:    li a1, 16
404; CHECK-NEXT:  .LBB25_2:
405; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
406; CHECK-NEXT:    vfcvt.rtz.xu.f.v v8, v8, v0.t
407; CHECK-NEXT:    addi a1, a0, -16
408; CHECK-NEXT:    sltu a0, a0, a1
409; CHECK-NEXT:    addi a0, a0, -1
410; CHECK-NEXT:    and a0, a0, a1
411; CHECK-NEXT:    vmv1r.v v0, v24
412; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
413; CHECK-NEXT:    vfcvt.rtz.xu.f.v v16, v16, v0.t
414; CHECK-NEXT:    ret
415  %v = call <32 x i64> @llvm.vp.fptoui.v32i64.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl)
416  ret <32 x i64> %v
417}
418
419define <32 x i64> @vfptoui_v32i64_v32f64_unmasked(<32 x double> %va, i32 zeroext %evl) {
420; CHECK-LABEL: vfptoui_v32i64_v32f64_unmasked:
421; CHECK:       # %bb.0:
422; CHECK-NEXT:    li a2, 16
423; CHECK-NEXT:    mv a1, a0
424; CHECK-NEXT:    bltu a0, a2, .LBB26_2
425; CHECK-NEXT:  # %bb.1:
426; CHECK-NEXT:    li a1, 16
427; CHECK-NEXT:  .LBB26_2:
428; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
429; CHECK-NEXT:    vfcvt.rtz.xu.f.v v8, v8
430; CHECK-NEXT:    addi a1, a0, -16
431; CHECK-NEXT:    sltu a0, a0, a1
432; CHECK-NEXT:    addi a0, a0, -1
433; CHECK-NEXT:    and a0, a0, a1
434; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
435; CHECK-NEXT:    vfcvt.rtz.xu.f.v v16, v16
436; CHECK-NEXT:    ret
437  %v = call <32 x i64> @llvm.vp.fptoui.v32i64.v32f64(<32 x double> %va, <32 x i1> splat (i1 true), i32 %evl)
438  ret <32 x i64> %v
439}
440