1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH 3; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH 4; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN 5; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN 6 7declare <4 x i1> @llvm.vp.fptoui.v4i1.v4f16(<4 x half>, <4 x i1>, i32) 8 9define <4 x i1> @vfptoui_v4i1_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) { 10; ZVFH-LABEL: vfptoui_v4i1_v4f16: 11; ZVFH: # %bb.0: 12; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 13; ZVFH-NEXT: vfcvt.rtz.xu.f.v v8, v8, v0.t 14; ZVFH-NEXT: vmsne.vi v0, v8, 0, v0.t 15; ZVFH-NEXT: ret 16; 17; ZVFHMIN-LABEL: vfptoui_v4i1_v4f16: 18; ZVFHMIN: # %bb.0: 19; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 20; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 21; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma 22; ZVFHMIN-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t 23; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0, v0.t 24; ZVFHMIN-NEXT: ret 25 %v = call <4 x i1> @llvm.vp.fptoui.v4i1.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl) 26 ret <4 x i1> %v 27} 28 29define <4 x i1> @vfptoui_v4i1_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) { 30; ZVFH-LABEL: vfptoui_v4i1_v4f16_unmasked: 31; ZVFH: # %bb.0: 32; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 33; ZVFH-NEXT: vfcvt.rtz.xu.f.v v8, v8 34; ZVFH-NEXT: vmsne.vi v0, v8, 0 35; ZVFH-NEXT: ret 36; 37; ZVFHMIN-LABEL: vfptoui_v4i1_v4f16_unmasked: 38; ZVFHMIN: # %bb.0: 39; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 40; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 41; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma 42; ZVFHMIN-NEXT: vfcvt.rtz.xu.f.v v8, v9 43; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0 44; ZVFHMIN-NEXT: ret 45 %v = call <4 x i1> @llvm.vp.fptoui.v4i1.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl) 46 ret <4 x i1> %v 47} 48 49declare <4 x i1> @llvm.vp.fptoui.v4i1.v4f32(<4 x float>, <4 x i1>, i32) 50 51define <4 x i1> @vfptoui_v4i1_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %evl) { 52; CHECK-LABEL: vfptoui_v4i1_v4f32: 53; CHECK: # %bb.0: 54; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 55; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8, v0.t 56; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t 57; CHECK-NEXT: ret 58 %v = call <4 x i1> @llvm.vp.fptoui.v4i1.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl) 59 ret <4 x i1> %v 60} 61 62define <4 x i1> @vfptoui_v4i1_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) { 63; CHECK-LABEL: vfptoui_v4i1_v4f32_unmasked: 64; CHECK: # %bb.0: 65; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 66; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 67; CHECK-NEXT: vmsne.vi v0, v8, 0 68; CHECK-NEXT: ret 69 %v = call <4 x i1> @llvm.vp.fptoui.v4i1.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl) 70 ret <4 x i1> %v 71} 72 73declare <4 x i1> @llvm.vp.fptoui.v4i1.v4f64(<4 x double>, <4 x i1>, i32) 74 75define <4 x i1> @vfptoui_v4i1_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %evl) { 76; CHECK-LABEL: vfptoui_v4i1_v4f64: 77; CHECK: # %bb.0: 78; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma 79; CHECK-NEXT: vfcvt.rtz.xu.f.v v10, v8, v0.t 80; CHECK-NEXT: vmsne.vi v8, v10, 0, v0.t 81; CHECK-NEXT: vmv1r.v v0, v8 82; CHECK-NEXT: ret 83 %v = call <4 x i1> @llvm.vp.fptoui.v4i1.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl) 84 ret <4 x i1> %v 85} 86 87define <4 x i1> @vfptoui_v4i1_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) { 88; CHECK-LABEL: vfptoui_v4i1_v4f64_unmasked: 89; CHECK: # %bb.0: 90; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma 91; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 92; CHECK-NEXT: vmsne.vi v0, v8, 0 93; CHECK-NEXT: ret 94 %v = call <4 x i1> @llvm.vp.fptoui.v4i1.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl) 95 ret <4 x i1> %v 96} 97