1# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2# NOTE: Assertions gave been autogenerated by utils/update_llc_test_checks.py 3# RUN: llc -mtriple riscv64 -mattr=+v -target-abi=lp64 -start-before=prologepilog -o - \ 4# RUN: -verify-machineinstrs %s | FileCheck %s 5--- | 6 target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" 7 target triple = "riscv64" 8 9 define weak_odr dso_local void @fixedlen_vector_spillslot(ptr %ay) nounwind { 10 ; CHECK-LABEL: fixedlen_vector_spillslot: 11 ; CHECK: # %bb.0: # %entry 12 ; CHECK-NEXT: addi sp, sp, -48 13 ; CHECK-NEXT: sd ra, 40(sp) # 8-byte Folded Spill 14 ; CHECK-NEXT: sd a0, 32(sp) 15 ; CHECK-NEXT: sd a0, 16(sp) 16 ; CHECK-NEXT: vsetivli a5, 1, e16, m1, ta, mu 17 ; CHECK-NEXT: sd a1, 0(sp) 18 ; CHECK-NEXT: addi a1, sp, 24 19 ; CHECK-NEXT: vs1r.v v25, (a1) # Unknown-size Folded Spill 20 ; CHECK-NEXT: ld a1, 0(sp) 21 ; CHECK-NEXT: call fixedlen_vector_spillslot 22 ; CHECK-NEXT: ld ra, 40(sp) # 8-byte Folded Reload 23 ; CHECK-NEXT: addi sp, sp, 48 24 ; CHECK-NEXT: ret 25 entry: 26 ret void 27 } 28 29... 30--- 31name: fixedlen_vector_spillslot 32alignment: 2 33tracksRegLiveness: false 34fixedStack: [] 35stack: 36 - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, 37 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 38 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 39 - { id: 1, name: '', type: spill-slot, offset: 0, size: 2, alignment: 8, 40 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 41 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 42 - { id: 2, name: '', type: default, offset: 0, size: 8, alignment: 8, 43 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 44 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 45body: | 46 bb.0.entry: 47 liveins: $x1, $x5, $x6, $x7, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x28, $x29, $x30, $x31, $v25 48 49 SD $x10, %stack.0, 0 50 SD $x10, %stack.2, 0 51 dead renamable $x15 = PseudoVSETIVLI 1, 72, implicit-def $vl, implicit-def $vtype 52 VS1R_V killed renamable $v25, %stack.1 :: (store unknown-size into %stack.1, align 8) 53 ; This is here just to make all the eligible registers live at this point. 54 ; This way when we replace the frame index %stack.1 with its actual address 55 ; we have to allocate a virtual register to compute it. 56 ; A later run of the the register scavenger won't find an available register 57 ; either so it will have to spill one to the emergency spill slot. 58 PseudoCALL target-flags(riscv-call) @fixedlen_vector_spillslot, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x31 59 PseudoRET 60... 61