xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
4
5define i1 @extractelt_nxv1i1(ptr %x, i64 %idx) nounwind {
6; CHECK-LABEL: extractelt_nxv1i1:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetvli a2, zero, e8, mf8, ta, ma
9; CHECK-NEXT:    vle8.v v8, (a0)
10; CHECK-NEXT:    vmseq.vi v0, v8, 0
11; CHECK-NEXT:    vmv.v.i v8, 0
12; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
13; CHECK-NEXT:    vslidedown.vx v8, v8, a1
14; CHECK-NEXT:    vmv.x.s a0, v8
15; CHECK-NEXT:    ret
16  %a = load <vscale x 1 x i8>, ptr %x
17  %b = icmp eq <vscale x 1 x i8> %a, zeroinitializer
18  %c = extractelement <vscale x 1 x i1> %b, i64 %idx
19  ret i1 %c
20}
21
22define i1 @extractelt_nxv2i1(ptr %x, i64 %idx) nounwind {
23; CHECK-LABEL: extractelt_nxv2i1:
24; CHECK:       # %bb.0:
25; CHECK-NEXT:    vsetvli a2, zero, e8, mf4, ta, ma
26; CHECK-NEXT:    vle8.v v8, (a0)
27; CHECK-NEXT:    vmseq.vi v0, v8, 0
28; CHECK-NEXT:    vmv.v.i v8, 0
29; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
30; CHECK-NEXT:    vslidedown.vx v8, v8, a1
31; CHECK-NEXT:    vmv.x.s a0, v8
32; CHECK-NEXT:    ret
33  %a = load <vscale x 2 x i8>, ptr %x
34  %b = icmp eq <vscale x 2 x i8> %a, zeroinitializer
35  %c = extractelement <vscale x 2 x i1> %b, i64 %idx
36  ret i1 %c
37}
38
39define i1 @extractelt_nxv4i1(ptr %x, i64 %idx) nounwind {
40; CHECK-LABEL: extractelt_nxv4i1:
41; CHECK:       # %bb.0:
42; CHECK-NEXT:    vsetvli a2, zero, e8, mf2, ta, ma
43; CHECK-NEXT:    vle8.v v8, (a0)
44; CHECK-NEXT:    vmseq.vi v0, v8, 0
45; CHECK-NEXT:    vmv.v.i v8, 0
46; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
47; CHECK-NEXT:    vslidedown.vx v8, v8, a1
48; CHECK-NEXT:    vmv.x.s a0, v8
49; CHECK-NEXT:    ret
50  %a = load <vscale x 4 x i8>, ptr %x
51  %b = icmp eq <vscale x 4 x i8> %a, zeroinitializer
52  %c = extractelement <vscale x 4 x i1> %b, i64 %idx
53  ret i1 %c
54}
55
56define i1 @extractelt_nxv8i1(ptr %x, i64 %idx) nounwind {
57; CHECK-LABEL: extractelt_nxv8i1:
58; CHECK:       # %bb.0:
59; CHECK-NEXT:    vl1r.v v8, (a0)
60; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
61; CHECK-NEXT:    vmseq.vi v0, v8, 0
62; CHECK-NEXT:    vmv.v.i v8, 0
63; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
64; CHECK-NEXT:    vslidedown.vx v8, v8, a1
65; CHECK-NEXT:    vmv.x.s a0, v8
66; CHECK-NEXT:    ret
67  %a = load <vscale x 8 x i8>, ptr %x
68  %b = icmp eq <vscale x 8 x i8> %a, zeroinitializer
69  %c = extractelement <vscale x 8 x i1> %b, i64 %idx
70  ret i1 %c
71}
72
73define i1 @extractelt_nxv16i1(ptr %x, i64 %idx) nounwind {
74; CHECK-LABEL: extractelt_nxv16i1:
75; CHECK:       # %bb.0:
76; CHECK-NEXT:    vl2r.v v8, (a0)
77; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
78; CHECK-NEXT:    vmseq.vi v0, v8, 0
79; CHECK-NEXT:    vmv.v.i v8, 0
80; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
81; CHECK-NEXT:    vslidedown.vx v8, v8, a1
82; CHECK-NEXT:    vmv.x.s a0, v8
83; CHECK-NEXT:    ret
84  %a = load <vscale x 16 x i8>, ptr %x
85  %b = icmp eq <vscale x 16 x i8> %a, zeroinitializer
86  %c = extractelement <vscale x 16 x i1> %b, i64 %idx
87  ret i1 %c
88}
89
90define i1 @extractelt_nxv32i1(ptr %x, i64 %idx) nounwind {
91; CHECK-LABEL: extractelt_nxv32i1:
92; CHECK:       # %bb.0:
93; CHECK-NEXT:    vl4r.v v8, (a0)
94; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
95; CHECK-NEXT:    vmseq.vi v0, v8, 0
96; CHECK-NEXT:    vmv.v.i v8, 0
97; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
98; CHECK-NEXT:    vslidedown.vx v8, v8, a1
99; CHECK-NEXT:    vmv.x.s a0, v8
100; CHECK-NEXT:    ret
101  %a = load <vscale x 32 x i8>, ptr %x
102  %b = icmp eq <vscale x 32 x i8> %a, zeroinitializer
103  %c = extractelement <vscale x 32 x i1> %b, i64 %idx
104  ret i1 %c
105}
106
107define i1 @extractelt_nxv64i1(ptr %x, i64 %idx) nounwind {
108; CHECK-LABEL: extractelt_nxv64i1:
109; CHECK:       # %bb.0:
110; CHECK-NEXT:    vl8r.v v8, (a0)
111; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
112; CHECK-NEXT:    vmseq.vi v0, v8, 0
113; CHECK-NEXT:    vmv.v.i v8, 0
114; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
115; CHECK-NEXT:    vslidedown.vx v8, v8, a1
116; CHECK-NEXT:    vmv.x.s a0, v8
117; CHECK-NEXT:    ret
118  %a = load <vscale x 64 x i8>, ptr %x
119  %b = icmp eq <vscale x 64 x i8> %a, zeroinitializer
120  %c = extractelement <vscale x 64 x i1> %b, i64 %idx
121  ret i1 %c
122}
123
124define i1 @extractelt_nxv128i1(ptr %x, i64 %idx) nounwind {
125; RV32-LABEL: extractelt_nxv128i1:
126; RV32:       # %bb.0:
127; RV32-NEXT:    csrr a2, vlenb
128; RV32-NEXT:    slli a3, a2, 4
129; RV32-NEXT:    addi a3, a3, -1
130; RV32-NEXT:    bltu a1, a3, .LBB7_2
131; RV32-NEXT:  # %bb.1:
132; RV32-NEXT:    mv a1, a3
133; RV32-NEXT:  .LBB7_2:
134; RV32-NEXT:    addi sp, sp, -80
135; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill
136; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill
137; RV32-NEXT:    addi s0, sp, 80
138; RV32-NEXT:    csrr a3, vlenb
139; RV32-NEXT:    slli a3, a3, 4
140; RV32-NEXT:    sub sp, sp, a3
141; RV32-NEXT:    andi sp, sp, -64
142; RV32-NEXT:    addi a3, sp, 64
143; RV32-NEXT:    vl8r.v v8, (a0)
144; RV32-NEXT:    slli a2, a2, 3
145; RV32-NEXT:    add a0, a0, a2
146; RV32-NEXT:    vl8r.v v24, (a0)
147; RV32-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
148; RV32-NEXT:    vmseq.vi v0, v8, 0
149; RV32-NEXT:    vmv.v.i v16, 0
150; RV32-NEXT:    add a1, a3, a1
151; RV32-NEXT:    add a2, a3, a2
152; RV32-NEXT:    vmseq.vi v8, v24, 0
153; RV32-NEXT:    vmerge.vim v24, v16, 1, v0
154; RV32-NEXT:    vs8r.v v24, (a3)
155; RV32-NEXT:    vmv1r.v v0, v8
156; RV32-NEXT:    vmerge.vim v8, v16, 1, v0
157; RV32-NEXT:    vs8r.v v8, (a2)
158; RV32-NEXT:    lbu a0, 0(a1)
159; RV32-NEXT:    addi sp, s0, -80
160; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload
161; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload
162; RV32-NEXT:    addi sp, sp, 80
163; RV32-NEXT:    ret
164;
165; RV64-LABEL: extractelt_nxv128i1:
166; RV64:       # %bb.0:
167; RV64-NEXT:    csrr a2, vlenb
168; RV64-NEXT:    slli a3, a2, 4
169; RV64-NEXT:    addi a3, a3, -1
170; RV64-NEXT:    bltu a1, a3, .LBB7_2
171; RV64-NEXT:  # %bb.1:
172; RV64-NEXT:    mv a1, a3
173; RV64-NEXT:  .LBB7_2:
174; RV64-NEXT:    addi sp, sp, -80
175; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill
176; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill
177; RV64-NEXT:    addi s0, sp, 80
178; RV64-NEXT:    csrr a3, vlenb
179; RV64-NEXT:    slli a3, a3, 4
180; RV64-NEXT:    sub sp, sp, a3
181; RV64-NEXT:    andi sp, sp, -64
182; RV64-NEXT:    addi a3, sp, 64
183; RV64-NEXT:    vl8r.v v8, (a0)
184; RV64-NEXT:    slli a2, a2, 3
185; RV64-NEXT:    add a0, a0, a2
186; RV64-NEXT:    vl8r.v v24, (a0)
187; RV64-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
188; RV64-NEXT:    vmseq.vi v0, v8, 0
189; RV64-NEXT:    vmv.v.i v16, 0
190; RV64-NEXT:    add a1, a3, a1
191; RV64-NEXT:    add a2, a3, a2
192; RV64-NEXT:    vmseq.vi v8, v24, 0
193; RV64-NEXT:    vmerge.vim v24, v16, 1, v0
194; RV64-NEXT:    vs8r.v v24, (a3)
195; RV64-NEXT:    vmv1r.v v0, v8
196; RV64-NEXT:    vmerge.vim v8, v16, 1, v0
197; RV64-NEXT:    vs8r.v v8, (a2)
198; RV64-NEXT:    lbu a0, 0(a1)
199; RV64-NEXT:    addi sp, s0, -80
200; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload
201; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload
202; RV64-NEXT:    addi sp, sp, 80
203; RV64-NEXT:    ret
204  %a = load <vscale x 128 x i8>, ptr %x
205  %b = icmp eq <vscale x 128 x i8> %a, zeroinitializer
206  %c = extractelement <vscale x 128 x i1> %b, i64 %idx
207  ret i1 %c
208}
209
210define i1 @extractelt_nxv1i1_idx0(ptr %x) nounwind {
211; CHECK-LABEL: extractelt_nxv1i1_idx0:
212; CHECK:       # %bb.0:
213; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
214; CHECK-NEXT:    vle8.v v8, (a0)
215; CHECK-NEXT:    vmseq.vi v8, v8, 0
216; CHECK-NEXT:    vfirst.m a0, v8
217; CHECK-NEXT:    seqz a0, a0
218; CHECK-NEXT:    ret
219  %a = load <vscale x 1 x i8>, ptr %x
220  %b = icmp eq <vscale x 1 x i8> %a, zeroinitializer
221  %c = extractelement <vscale x 1 x i1> %b, i64 0
222  ret i1 %c
223}
224
225define i1 @extractelt_nxv2i1_idx0(ptr %x) nounwind {
226; CHECK-LABEL: extractelt_nxv2i1_idx0:
227; CHECK:       # %bb.0:
228; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
229; CHECK-NEXT:    vle8.v v8, (a0)
230; CHECK-NEXT:    vmseq.vi v8, v8, 0
231; CHECK-NEXT:    vfirst.m a0, v8
232; CHECK-NEXT:    seqz a0, a0
233; CHECK-NEXT:    ret
234  %a = load <vscale x 2 x i8>, ptr %x
235  %b = icmp eq <vscale x 2 x i8> %a, zeroinitializer
236  %c = extractelement <vscale x 2 x i1> %b, i64 0
237  ret i1 %c
238}
239
240define i1 @extractelt_nxv4i1_idx0(ptr %x) nounwind {
241; CHECK-LABEL: extractelt_nxv4i1_idx0:
242; CHECK:       # %bb.0:
243; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
244; CHECK-NEXT:    vle8.v v8, (a0)
245; CHECK-NEXT:    vmseq.vi v8, v8, 0
246; CHECK-NEXT:    vfirst.m a0, v8
247; CHECK-NEXT:    seqz a0, a0
248; CHECK-NEXT:    ret
249  %a = load <vscale x 4 x i8>, ptr %x
250  %b = icmp eq <vscale x 4 x i8> %a, zeroinitializer
251  %c = extractelement <vscale x 4 x i1> %b, i64 0
252  ret i1 %c
253}
254
255define i1 @extractelt_nxv8i1_idx0(ptr %x) nounwind {
256; CHECK-LABEL: extractelt_nxv8i1_idx0:
257; CHECK:       # %bb.0:
258; CHECK-NEXT:    vl1r.v v8, (a0)
259; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
260; CHECK-NEXT:    vmseq.vi v8, v8, 0
261; CHECK-NEXT:    vfirst.m a0, v8
262; CHECK-NEXT:    seqz a0, a0
263; CHECK-NEXT:    ret
264  %a = load <vscale x 8 x i8>, ptr %x
265  %b = icmp eq <vscale x 8 x i8> %a, zeroinitializer
266  %c = extractelement <vscale x 8 x i1> %b, i64 0
267  ret i1 %c
268}
269
270define i1 @extractelt_nxv16i1_idx0(ptr %x) nounwind {
271; CHECK-LABEL: extractelt_nxv16i1_idx0:
272; CHECK:       # %bb.0:
273; CHECK-NEXT:    vl2r.v v8, (a0)
274; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
275; CHECK-NEXT:    vmseq.vi v10, v8, 0
276; CHECK-NEXT:    vfirst.m a0, v10
277; CHECK-NEXT:    seqz a0, a0
278; CHECK-NEXT:    ret
279  %a = load <vscale x 16 x i8>, ptr %x
280  %b = icmp eq <vscale x 16 x i8> %a, zeroinitializer
281  %c = extractelement <vscale x 16 x i1> %b, i64 0
282  ret i1 %c
283}
284
285define i1 @extractelt_nxv32i1_idx0(ptr %x) nounwind {
286; CHECK-LABEL: extractelt_nxv32i1_idx0:
287; CHECK:       # %bb.0:
288; CHECK-NEXT:    vl4r.v v8, (a0)
289; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
290; CHECK-NEXT:    vmseq.vi v12, v8, 0
291; CHECK-NEXT:    vfirst.m a0, v12
292; CHECK-NEXT:    seqz a0, a0
293; CHECK-NEXT:    ret
294  %a = load <vscale x 32 x i8>, ptr %x
295  %b = icmp eq <vscale x 32 x i8> %a, zeroinitializer
296  %c = extractelement <vscale x 32 x i1> %b, i64 0
297  ret i1 %c
298}
299
300define i1 @extractelt_nxv64i1_idx0(ptr %x) nounwind {
301; CHECK-LABEL: extractelt_nxv64i1_idx0:
302; CHECK:       # %bb.0:
303; CHECK-NEXT:    vl8r.v v8, (a0)
304; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
305; CHECK-NEXT:    vmseq.vi v16, v8, 0
306; CHECK-NEXT:    vfirst.m a0, v16
307; CHECK-NEXT:    seqz a0, a0
308; CHECK-NEXT:    ret
309  %a = load <vscale x 64 x i8>, ptr %x
310  %b = icmp eq <vscale x 64 x i8> %a, zeroinitializer
311  %c = extractelement <vscale x 64 x i1> %b, i64 0
312  ret i1 %c
313}
314