1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32 3; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64 4; Should expand to scalar instructions and do not crash 5 6declare i32 @llvm.vp.reduce.add.v4i32(i32, <4 x i32>, <4 x i1>, i32) 7 8define i32 @vpreduce_add_v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl) { 9; RV32-LABEL: vpreduce_add_v4i32: 10; RV32: # %bb.0: 11; RV32-NEXT: lw a4, 0(a1) 12; RV32-NEXT: lw a5, 4(a1) 13; RV32-NEXT: lw a6, 8(a1) 14; RV32-NEXT: lw a1, 12(a1) 15; RV32-NEXT: lw a7, 0(a2) 16; RV32-NEXT: lw t0, 4(a2) 17; RV32-NEXT: lw t1, 8(a2) 18; RV32-NEXT: lw a2, 12(a2) 19; RV32-NEXT: snez t2, a3 20; RV32-NEXT: sltiu t3, a3, 3 21; RV32-NEXT: sltiu t4, a3, 4 22; RV32-NEXT: sltiu a3, a3, 2 23; RV32-NEXT: xori t3, t3, 1 24; RV32-NEXT: xori t4, t4, 1 25; RV32-NEXT: xori a3, a3, 1 26; RV32-NEXT: and a3, a3, t0 27; RV32-NEXT: and a2, t4, a2 28; RV32-NEXT: and t0, t3, t1 29; RV32-NEXT: and a7, t2, a7 30; RV32-NEXT: neg a7, a7 31; RV32-NEXT: neg t0, t0 32; RV32-NEXT: neg a2, a2 33; RV32-NEXT: neg a3, a3 34; RV32-NEXT: and a4, a7, a4 35; RV32-NEXT: and a6, t0, a6 36; RV32-NEXT: and a1, a2, a1 37; RV32-NEXT: and a3, a3, a5 38; RV32-NEXT: add a1, a3, a1 39; RV32-NEXT: add a4, a4, a6 40; RV32-NEXT: add a1, a4, a1 41; RV32-NEXT: add a0, a1, a0 42; RV32-NEXT: ret 43; 44; RV64-LABEL: vpreduce_add_v4i32: 45; RV64: # %bb.0: 46; RV64-NEXT: lw a4, 0(a1) 47; RV64-NEXT: lw a5, 8(a1) 48; RV64-NEXT: lw a6, 16(a1) 49; RV64-NEXT: lw a1, 24(a1) 50; RV64-NEXT: ld a7, 0(a2) 51; RV64-NEXT: ld t0, 8(a2) 52; RV64-NEXT: ld t1, 16(a2) 53; RV64-NEXT: ld a2, 24(a2) 54; RV64-NEXT: sext.w a3, a3 55; RV64-NEXT: snez t2, a3 56; RV64-NEXT: sltiu t3, a3, 3 57; RV64-NEXT: sltiu t4, a3, 4 58; RV64-NEXT: sltiu a3, a3, 2 59; RV64-NEXT: xori t3, t3, 1 60; RV64-NEXT: xori t4, t4, 1 61; RV64-NEXT: xori a3, a3, 1 62; RV64-NEXT: and a3, a3, t0 63; RV64-NEXT: and a2, t4, a2 64; RV64-NEXT: and t0, t3, t1 65; RV64-NEXT: and a7, t2, a7 66; RV64-NEXT: negw a7, a7 67; RV64-NEXT: negw t0, t0 68; RV64-NEXT: negw a2, a2 69; RV64-NEXT: negw a3, a3 70; RV64-NEXT: and a4, a7, a4 71; RV64-NEXT: and a6, t0, a6 72; RV64-NEXT: and a1, a2, a1 73; RV64-NEXT: and a3, a3, a5 74; RV64-NEXT: add a1, a3, a1 75; RV64-NEXT: add a4, a4, a6 76; RV64-NEXT: add a1, a4, a1 77; RV64-NEXT: addw a0, a1, a0 78; RV64-NEXT: ret 79 %r = call i32 @llvm.vp.reduce.add.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl) 80 ret i32 %r 81} 82