xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir (revision cc9ba5600e540fd4e059d20591917962a6df043d)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=register-coalescer %s -o - 2>&1 | FileCheck %s
3
4# This test used to crash in the register coalescer when the target would
5# return the out-of-bounds CommuteAnyOperandIndex for one of its commutable
6# operand indices.
7
8--- |
9  target triple = "riscv64"
10  target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
11
12  define void @commuted_op_indices() {
13    unreachable
14  }
15...
16---
17name:            commuted_op_indices
18tracksRegLiveness: true
19registers:
20  - { id: 0, class: vr, preferred-register: '' }
21  - { id: 1, class: vrnov0, preferred-register: '' }
22  - { id: 2, class: vrnov0, preferred-register: '' }
23  - { id: 3, class: vr, preferred-register: '' }
24body:             |
25  bb.0:
26    liveins: $v0, $v1, $v2
27    ; CHECK-LABEL: name: commuted_op_indices
28    ; CHECK: liveins: $v0, $v1, $v2
29    ; CHECK-NEXT: {{  $}}
30    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v0
31    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrnov0 = COPY $v1
32    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrnov0 = COPY $v2
33    ; CHECK-NEXT: [[PseudoVNMSUB_VV_M1_:%[0-9]+]]:vr = PseudoVNMSUB_VV_M1 [[PseudoVNMSUB_VV_M1_]], [[COPY1]], [[COPY2]], -1, 6 /* e64 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
34    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY [[PseudoVNMSUB_VV_M1_]]
35    ; CHECK-NEXT: dead [[PseudoVSLL_VI_M1_:%[0-9]+]]:vr = PseudoVSLL_VI_M1 undef [[PseudoVSLL_VI_M1_]], [[PseudoVSLL_VI_M1_]], 11, $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
36    ; CHECK-NEXT: $v0 = COPY [[PseudoVNMSUB_VV_M1_]]
37    ; CHECK-NEXT: PseudoRET implicit $v0
38    %0:vr = COPY $v0
39    %1:vrnov0 = COPY $v1
40    %2:vrnov0 = COPY $v2
41    %0:vr = PseudoVNMSUB_VV_M1 %0, %1, killed %2, -1, 6, 1, implicit $vl, implicit $vtype
42    %3:vr = COPY %0
43    %3:vr = PseudoVSLL_VI_M1 undef %3, %3, 11, $noreg, 6, 0, implicit $vl, implicit $vtype
44    $v0 = COPY %0
45    PseudoRET implicit $v0
46...
47