xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll (revision 97982a8c605fac7c86d02e641a6cd7898b3ca343) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+m -mattr=+v -O2 < %s \
3; RUN:    | FileCheck --check-prefix=SPILL-O2 %s
4
5define <vscale x 1 x i32> @test_vector_std(<vscale x 1 x i32> %va) nounwind {
6; SPILL-O2-LABEL: test_vector_std:
7; SPILL-O2:       # %bb.0: # %entry
8; SPILL-O2-NEXT:    addi sp, sp, -16
9; SPILL-O2-NEXT:    csrr a0, vlenb
10; SPILL-O2-NEXT:    sub sp, sp, a0
11; SPILL-O2-NEXT:    addi a0, sp, 16
12; SPILL-O2-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
13; SPILL-O2-NEXT:    #APP
14; SPILL-O2-NEXT:    #NO_APP
15; SPILL-O2-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
16; SPILL-O2-NEXT:    csrr a0, vlenb
17; SPILL-O2-NEXT:    add sp, sp, a0
18; SPILL-O2-NEXT:    addi sp, sp, 16
19; SPILL-O2-NEXT:    ret
20entry:
21  call void asm sideeffect "",
22  "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
23
24  ret <vscale x 1 x i32> %va
25}
26
27define riscv_vector_cc <vscale x 1 x i32> @test_vector_callee(<vscale x 1 x i32> %va) nounwind {
28; SPILL-O2-LABEL: test_vector_callee:
29; SPILL-O2:       # %bb.0: # %entry
30; SPILL-O2-NEXT:    addi sp, sp, -16
31; SPILL-O2-NEXT:    csrr a0, vlenb
32; SPILL-O2-NEXT:    slli a0, a0, 4
33; SPILL-O2-NEXT:    sub sp, sp, a0
34; SPILL-O2-NEXT:    csrr a0, vlenb
35; SPILL-O2-NEXT:    slli a1, a0, 4
36; SPILL-O2-NEXT:    sub a0, a1, a0
37; SPILL-O2-NEXT:    add a0, sp, a0
38; SPILL-O2-NEXT:    addi a0, a0, 16
39; SPILL-O2-NEXT:    vs1r.v v1, (a0) # Unknown-size Folded Spill
40; SPILL-O2-NEXT:    csrr a0, vlenb
41; SPILL-O2-NEXT:    li a1, 13
42; SPILL-O2-NEXT:    mul a0, a0, a1
43; SPILL-O2-NEXT:    add a0, sp, a0
44; SPILL-O2-NEXT:    addi a0, a0, 16
45; SPILL-O2-NEXT:    vs2r.v v2, (a0) # Unknown-size Folded Spill
46; SPILL-O2-NEXT:    csrr a0, vlenb
47; SPILL-O2-NEXT:    slli a1, a0, 3
48; SPILL-O2-NEXT:    add a0, a1, a0
49; SPILL-O2-NEXT:    add a0, sp, a0
50; SPILL-O2-NEXT:    addi a0, a0, 16
51; SPILL-O2-NEXT:    vs4r.v v4, (a0) # Unknown-size Folded Spill
52; SPILL-O2-NEXT:    csrr a0, vlenb
53; SPILL-O2-NEXT:    add a0, sp, a0
54; SPILL-O2-NEXT:    addi a0, a0, 16
55; SPILL-O2-NEXT:    vs8r.v v24, (a0) # Unknown-size Folded Spill
56; SPILL-O2-NEXT:    addi a0, sp, 16
57; SPILL-O2-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
58; SPILL-O2-NEXT:    #APP
59; SPILL-O2-NEXT:    #NO_APP
60; SPILL-O2-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
61; SPILL-O2-NEXT:    csrr a0, vlenb
62; SPILL-O2-NEXT:    slli a1, a0, 4
63; SPILL-O2-NEXT:    sub a0, a1, a0
64; SPILL-O2-NEXT:    add a0, sp, a0
65; SPILL-O2-NEXT:    addi a0, a0, 16
66; SPILL-O2-NEXT:    vl1r.v v1, (a0) # Unknown-size Folded Reload
67; SPILL-O2-NEXT:    csrr a0, vlenb
68; SPILL-O2-NEXT:    li a1, 13
69; SPILL-O2-NEXT:    mul a0, a0, a1
70; SPILL-O2-NEXT:    add a0, sp, a0
71; SPILL-O2-NEXT:    addi a0, a0, 16
72; SPILL-O2-NEXT:    vl2r.v v2, (a0) # Unknown-size Folded Reload
73; SPILL-O2-NEXT:    csrr a0, vlenb
74; SPILL-O2-NEXT:    slli a1, a0, 3
75; SPILL-O2-NEXT:    add a0, a1, a0
76; SPILL-O2-NEXT:    add a0, sp, a0
77; SPILL-O2-NEXT:    addi a0, a0, 16
78; SPILL-O2-NEXT:    vl4r.v v4, (a0) # Unknown-size Folded Reload
79; SPILL-O2-NEXT:    csrr a0, vlenb
80; SPILL-O2-NEXT:    add a0, sp, a0
81; SPILL-O2-NEXT:    addi a0, a0, 16
82; SPILL-O2-NEXT:    vl8r.v v24, (a0) # Unknown-size Folded Reload
83; SPILL-O2-NEXT:    csrr a0, vlenb
84; SPILL-O2-NEXT:    slli a0, a0, 4
85; SPILL-O2-NEXT:    add sp, sp, a0
86; SPILL-O2-NEXT:    addi sp, sp, 16
87; SPILL-O2-NEXT:    ret
88entry:
89  call void asm sideeffect "",
90  "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
91
92  ret <vscale x 1 x i32> %va
93}
94
95; Make sure the local stack allocation pass doesn't count vector registers. The
96; sizes are chosen to be on the edge of what RISCVRegister::needsFrameBaseReg
97; considers to need a virtual base register.
98define riscv_vector_cc void @local_stack_allocation_frame_pointer() "frame-pointer"="all" {
99; SPILL-O2-LABEL: local_stack_allocation_frame_pointer:
100; SPILL-O2:       # %bb.0:
101; SPILL-O2-NEXT:    addi sp, sp, -2032
102; SPILL-O2-NEXT:    .cfi_def_cfa_offset 2032
103; SPILL-O2-NEXT:    sw ra, 2028(sp) # 4-byte Folded Spill
104; SPILL-O2-NEXT:    sw s0, 2024(sp) # 4-byte Folded Spill
105; SPILL-O2-NEXT:    .cfi_offset ra, -4
106; SPILL-O2-NEXT:    .cfi_offset s0, -8
107; SPILL-O2-NEXT:    addi s0, sp, 2032
108; SPILL-O2-NEXT:    .cfi_def_cfa s0, 0
109; SPILL-O2-NEXT:    addi sp, sp, -480
110; SPILL-O2-NEXT:    lbu a0, -1912(s0)
111; SPILL-O2-NEXT:    sb a0, -1912(s0)
112; SPILL-O2-NEXT:    addi sp, s0, -2032
113; SPILL-O2-NEXT:    .cfi_def_cfa sp, 2032
114; SPILL-O2-NEXT:    lw ra, 2028(sp) # 4-byte Folded Reload
115; SPILL-O2-NEXT:    lw s0, 2024(sp) # 4-byte Folded Reload
116; SPILL-O2-NEXT:    .cfi_restore ra
117; SPILL-O2-NEXT:    .cfi_restore s0
118; SPILL-O2-NEXT:    addi sp, sp, 2032
119; SPILL-O2-NEXT:    .cfi_def_cfa_offset 0
120; SPILL-O2-NEXT:    ret
121  %va = alloca [2500 x i8], align 4
122  %va_gep = getelementptr [2000 x i8], ptr %va, i64 0, i64 600
123  %load = load volatile i8, ptr %va_gep, align 4
124  store volatile i8 %load, ptr %va_gep, align 4
125  ret void
126}
127