xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/binop-zext.ll (revision a3c2d8c0720424579c2a9b6313664908db7fcb14) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
4
5; Check that we perform binary arithmetic in a narrower type where possible, via
6; combineBinOpOfZExt or otherwise.
7
8define <vscale x 8 x i32> @add(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
9; CHECK-LABEL: add:
10; CHECK:       # %bb.0:
11; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
12; CHECK-NEXT:    vwaddu.vv v12, v8, v9
13; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
14; CHECK-NEXT:    vzext.vf2 v8, v12
15; CHECK-NEXT:    ret
16  %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>
17  %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>
18  %add = add <vscale x 8 x i32> %a.zext, %b.zext
19  ret <vscale x 8 x i32> %add
20}
21
22define <vscale x 8 x i32> @sub(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
23; CHECK-LABEL: sub:
24; CHECK:       # %bb.0:
25; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
26; CHECK-NEXT:    vwsubu.vv v12, v8, v9
27; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
28; CHECK-NEXT:    vsext.vf2 v8, v12
29; CHECK-NEXT:    ret
30  %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>
31  %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>
32  %sub = sub <vscale x 8 x i32> %a.zext, %b.zext
33  ret <vscale x 8 x i32> %sub
34}
35
36define <vscale x 8 x i32> @mul(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
37; CHECK-LABEL: mul:
38; CHECK:       # %bb.0:
39; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
40; CHECK-NEXT:    vwmulu.vv v12, v8, v9
41; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
42; CHECK-NEXT:    vzext.vf2 v8, v12
43; CHECK-NEXT:    ret
44  %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>
45  %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>
46  %mul = mul <vscale x 8 x i32> %a.zext, %b.zext
47  ret <vscale x 8 x i32> %mul
48}
49
50define <vscale x 8 x i32> @sdiv(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
51; CHECK-LABEL: sdiv:
52; CHECK:       # %bb.0:
53; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
54; CHECK-NEXT:    vzext.vf2 v10, v9
55; CHECK-NEXT:    vzext.vf2 v12, v8
56; CHECK-NEXT:    vdivu.vv v12, v12, v10
57; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
58; CHECK-NEXT:    vzext.vf2 v8, v12
59; CHECK-NEXT:    ret
60  %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>
61  %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>
62  %sdiv = sdiv <vscale x 8 x i32> %a.zext, %b.zext
63  ret <vscale x 8 x i32> %sdiv
64}
65
66define <vscale x 8 x i32> @udiv(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
67; CHECK-LABEL: udiv:
68; CHECK:       # %bb.0:
69; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
70; CHECK-NEXT:    vzext.vf2 v10, v9
71; CHECK-NEXT:    vzext.vf2 v12, v8
72; CHECK-NEXT:    vdivu.vv v12, v12, v10
73; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
74; CHECK-NEXT:    vzext.vf2 v8, v12
75; CHECK-NEXT:    ret
76  %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>
77  %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>
78  %udiv = udiv <vscale x 8 x i32> %a.zext, %b.zext
79  ret <vscale x 8 x i32> %udiv
80}
81
82define <vscale x 8 x i32> @srem(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
83; CHECK-LABEL: srem:
84; CHECK:       # %bb.0:
85; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
86; CHECK-NEXT:    vzext.vf2 v10, v9
87; CHECK-NEXT:    vzext.vf2 v12, v8
88; CHECK-NEXT:    vremu.vv v12, v12, v10
89; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
90; CHECK-NEXT:    vzext.vf2 v8, v12
91; CHECK-NEXT:    ret
92  %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>
93  %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>
94  %srem = srem <vscale x 8 x i32> %a.zext, %b.zext
95  ret <vscale x 8 x i32> %srem
96}
97
98define <vscale x 8 x i32> @urem(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
99; CHECK-LABEL: urem:
100; CHECK:       # %bb.0:
101; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
102; CHECK-NEXT:    vzext.vf2 v10, v9
103; CHECK-NEXT:    vzext.vf2 v12, v8
104; CHECK-NEXT:    vremu.vv v12, v12, v10
105; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
106; CHECK-NEXT:    vzext.vf2 v8, v12
107; CHECK-NEXT:    ret
108  %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>
109  %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>
110  %urem = urem <vscale x 8 x i32> %a.zext, %b.zext
111  ret <vscale x 8 x i32> %urem
112}
113
114define <vscale x 8 x i32> @and(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
115; CHECK-LABEL: and:
116; CHECK:       # %bb.0:
117; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
118; CHECK-NEXT:    vand.vv v12, v8, v9
119; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
120; CHECK-NEXT:    vzext.vf4 v8, v12
121; CHECK-NEXT:    ret
122  %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>
123  %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>
124  %shl = and <vscale x 8 x i32> %a.zext, %b.zext
125  ret <vscale x 8 x i32> %shl
126}
127
128define <vscale x 8 x i32> @or(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
129; CHECK-LABEL: or:
130; CHECK:       # %bb.0:
131; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
132; CHECK-NEXT:    vor.vv v12, v8, v9
133; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
134; CHECK-NEXT:    vzext.vf4 v8, v12
135; CHECK-NEXT:    ret
136  %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>
137  %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>
138  %or = or <vscale x 8 x i32> %a.zext, %b.zext
139  ret <vscale x 8 x i32> %or
140}
141
142define <vscale x 8 x i32> @xor(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
143; CHECK-LABEL: xor:
144; CHECK:       # %bb.0:
145; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
146; CHECK-NEXT:    vxor.vv v12, v8, v9
147; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
148; CHECK-NEXT:    vzext.vf4 v8, v12
149; CHECK-NEXT:    ret
150  %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>
151  %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>
152  %xor = xor <vscale x 8 x i32> %a.zext, %b.zext
153  ret <vscale x 8 x i32> %xor
154}
155