1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefixes=RV64I 4; RUN: llc -mtriple=riscv64 -mattr=+xtheadbs -verify-machineinstrs < %s \ 5; RUN: | FileCheck %s -check-prefixes=RV64XTHEADBS 6 7define signext i32 @th_tst_i32(i32 signext %a) nounwind { 8; RV64I-LABEL: th_tst_i32: 9; RV64I: # %bb.0: 10; RV64I-NEXT: slli a0, a0, 58 11; RV64I-NEXT: srli a0, a0, 63 12; RV64I-NEXT: ret 13; 14; RV64XTHEADBS-LABEL: th_tst_i32: 15; RV64XTHEADBS: # %bb.0: 16; RV64XTHEADBS-NEXT: th.tst a0, a0, 5 17; RV64XTHEADBS-NEXT: ret 18 %shr = lshr i32 %a, 5 19 %and = and i32 %shr, 1 20 ret i32 %and 21} 22 23define i64 @the_tst_i64(i64 %a) nounwind { 24; RV64I-LABEL: the_tst_i64: 25; RV64I: # %bb.0: 26; RV64I-NEXT: slli a0, a0, 58 27; RV64I-NEXT: srli a0, a0, 63 28; RV64I-NEXT: ret 29; 30; RV64XTHEADBS-LABEL: the_tst_i64: 31; RV64XTHEADBS: # %bb.0: 32; RV64XTHEADBS-NEXT: th.tst a0, a0, 5 33; RV64XTHEADBS-NEXT: ret 34 %shr = lshr i64 %a, 5 35 %and = and i64 %shr, 1 36 ret i64 %and 37} 38 39define signext i32 @th_tst_i32_cmp(i32 signext %a) nounwind { 40; RV64I-LABEL: th_tst_i32_cmp: 41; RV64I: # %bb.0: 42; RV64I-NEXT: slli a0, a0, 58 43; RV64I-NEXT: srli a0, a0, 63 44; RV64I-NEXT: ret 45; 46; RV64XTHEADBS-LABEL: th_tst_i32_cmp: 47; RV64XTHEADBS: # %bb.0: 48; RV64XTHEADBS-NEXT: th.tst a0, a0, 5 49; RV64XTHEADBS-NEXT: ret 50 %and = and i32 %a, 32 51 %cmp = icmp ne i32 %and, 0 52 %zext = zext i1 %cmp to i32 53 ret i32 %zext 54} 55 56define i64 @th_tst_i64_cmp(i64 %a) nounwind { 57; RV64I-LABEL: th_tst_i64_cmp: 58; RV64I: # %bb.0: 59; RV64I-NEXT: slli a0, a0, 58 60; RV64I-NEXT: srli a0, a0, 63 61; RV64I-NEXT: ret 62; 63; RV64XTHEADBS-LABEL: th_tst_i64_cmp: 64; RV64XTHEADBS: # %bb.0: 65; RV64XTHEADBS-NEXT: th.tst a0, a0, 5 66; RV64XTHEADBS-NEXT: ret 67 %and = and i64 %a, 32 68 %cmp = icmp ne i64 %and, 0 69 %zext = zext i1 %cmp to i64 70 ret i64 %zext 71} 72