xref: /llvm-project/llvm/test/CodeGen/RISCV/rv64e.ll (revision 3ac9fe69f70a2b3541266daedbaaa7dc9c007a2a)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -mtriple=riscv64 -mattr=+e -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s
4
5; TODO: Add more tests.
6
7define i64 @exhausted(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g) {
8; CHECK-LABEL: exhausted:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    ld t0, 0(sp)
11; CHECK-NEXT:    add a0, a0, a1
12; CHECK-NEXT:    add a2, a3, a2
13; CHECK-NEXT:    add a0, a2, a0
14; CHECK-NEXT:    add a4, a5, a4
15; CHECK-NEXT:    add a0, a4, a0
16; CHECK-NEXT:    add a0, t0, a0
17; CHECK-NEXT:    ret
18  %1 = add i64 %a, %b
19  %2 = add i64 %c, %1
20  %3 = add i64 %d, %2
21  %4 = add i64 %e, %3
22  %5 = add i64 %f, %4
23  %6 = add i64 %g, %5
24  ret i64 %6
25}
26