xref: /llvm-project/llvm/test/CodeGen/RISCV/rv32zba.ll (revision 949caf39e4a445cc0600735ac0755dd0d4aa28f6) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32I
4; RUN: llc -mtriple=riscv32 -mattr=+m,+zba -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32ZBA
6
7define signext i16 @sh1add(i64 %0, ptr %1) {
8; RV32I-LABEL: sh1add:
9; RV32I:       # %bb.0:
10; RV32I-NEXT:    slli a0, a0, 1
11; RV32I-NEXT:    add a0, a2, a0
12; RV32I-NEXT:    lh a0, 0(a0)
13; RV32I-NEXT:    ret
14;
15; RV32ZBA-LABEL: sh1add:
16; RV32ZBA:       # %bb.0:
17; RV32ZBA-NEXT:    sh1add a0, a0, a2
18; RV32ZBA-NEXT:    lh a0, 0(a0)
19; RV32ZBA-NEXT:    ret
20  %3 = getelementptr inbounds i16, ptr %1, i64 %0
21  %4 = load i16, ptr %3
22  ret i16 %4
23}
24
25define i32 @sh2add(i64 %0, ptr %1) {
26; RV32I-LABEL: sh2add:
27; RV32I:       # %bb.0:
28; RV32I-NEXT:    slli a0, a0, 2
29; RV32I-NEXT:    add a0, a2, a0
30; RV32I-NEXT:    lw a0, 0(a0)
31; RV32I-NEXT:    ret
32;
33; RV32ZBA-LABEL: sh2add:
34; RV32ZBA:       # %bb.0:
35; RV32ZBA-NEXT:    sh2add a0, a0, a2
36; RV32ZBA-NEXT:    lw a0, 0(a0)
37; RV32ZBA-NEXT:    ret
38  %3 = getelementptr inbounds i32, ptr %1, i64 %0
39  %4 = load i32, ptr %3
40  ret i32 %4
41}
42
43define i64 @sh3add(i64 %0, ptr %1) {
44; RV32I-LABEL: sh3add:
45; RV32I:       # %bb.0:
46; RV32I-NEXT:    slli a0, a0, 3
47; RV32I-NEXT:    add a2, a2, a0
48; RV32I-NEXT:    lw a0, 0(a2)
49; RV32I-NEXT:    lw a1, 4(a2)
50; RV32I-NEXT:    ret
51;
52; RV32ZBA-LABEL: sh3add:
53; RV32ZBA:       # %bb.0:
54; RV32ZBA-NEXT:    sh3add a1, a0, a2
55; RV32ZBA-NEXT:    lw a0, 0(a1)
56; RV32ZBA-NEXT:    lw a1, 4(a1)
57; RV32ZBA-NEXT:    ret
58  %3 = getelementptr inbounds i64, ptr %1, i64 %0
59  %4 = load i64, ptr %3
60  ret i64 %4
61}
62
63define i32 @addmul6(i32 %a, i32 %b) {
64; RV32I-LABEL: addmul6:
65; RV32I:       # %bb.0:
66; RV32I-NEXT:    slli a2, a0, 1
67; RV32I-NEXT:    slli a0, a0, 3
68; RV32I-NEXT:    sub a0, a0, a2
69; RV32I-NEXT:    add a0, a0, a1
70; RV32I-NEXT:    ret
71;
72; RV32ZBA-LABEL: addmul6:
73; RV32ZBA:       # %bb.0:
74; RV32ZBA-NEXT:    sh1add a0, a0, a0
75; RV32ZBA-NEXT:    sh1add a0, a0, a1
76; RV32ZBA-NEXT:    ret
77  %c = mul i32 %a, 6
78  %d = add i32 %c, %b
79  ret i32 %d
80}
81
82define i32 @addmul10(i32 %a, i32 %b) {
83; RV32I-LABEL: addmul10:
84; RV32I:       # %bb.0:
85; RV32I-NEXT:    li a2, 10
86; RV32I-NEXT:    mul a0, a0, a2
87; RV32I-NEXT:    add a0, a0, a1
88; RV32I-NEXT:    ret
89;
90; RV32ZBA-LABEL: addmul10:
91; RV32ZBA:       # %bb.0:
92; RV32ZBA-NEXT:    sh2add a0, a0, a0
93; RV32ZBA-NEXT:    sh1add a0, a0, a1
94; RV32ZBA-NEXT:    ret
95  %c = mul i32 %a, 10
96  %d = add i32 %c, %b
97  ret i32 %d
98}
99
100define i32 @addmul12(i32 %a, i32 %b) {
101; RV32I-LABEL: addmul12:
102; RV32I:       # %bb.0:
103; RV32I-NEXT:    slli a2, a0, 2
104; RV32I-NEXT:    slli a0, a0, 4
105; RV32I-NEXT:    sub a0, a0, a2
106; RV32I-NEXT:    add a0, a0, a1
107; RV32I-NEXT:    ret
108;
109; RV32ZBA-LABEL: addmul12:
110; RV32ZBA:       # %bb.0:
111; RV32ZBA-NEXT:    sh1add a0, a0, a0
112; RV32ZBA-NEXT:    sh2add a0, a0, a1
113; RV32ZBA-NEXT:    ret
114  %c = mul i32 %a, 12
115  %d = add i32 %c, %b
116  ret i32 %d
117}
118
119define i32 @addmul18(i32 %a, i32 %b) {
120; RV32I-LABEL: addmul18:
121; RV32I:       # %bb.0:
122; RV32I-NEXT:    li a2, 18
123; RV32I-NEXT:    mul a0, a0, a2
124; RV32I-NEXT:    add a0, a0, a1
125; RV32I-NEXT:    ret
126;
127; RV32ZBA-LABEL: addmul18:
128; RV32ZBA:       # %bb.0:
129; RV32ZBA-NEXT:    sh3add a0, a0, a0
130; RV32ZBA-NEXT:    sh1add a0, a0, a1
131; RV32ZBA-NEXT:    ret
132  %c = mul i32 %a, 18
133  %d = add i32 %c, %b
134  ret i32 %d
135}
136
137define i32 @addmul20(i32 %a, i32 %b) {
138; RV32I-LABEL: addmul20:
139; RV32I:       # %bb.0:
140; RV32I-NEXT:    li a2, 20
141; RV32I-NEXT:    mul a0, a0, a2
142; RV32I-NEXT:    add a0, a0, a1
143; RV32I-NEXT:    ret
144;
145; RV32ZBA-LABEL: addmul20:
146; RV32ZBA:       # %bb.0:
147; RV32ZBA-NEXT:    sh2add a0, a0, a0
148; RV32ZBA-NEXT:    sh2add a0, a0, a1
149; RV32ZBA-NEXT:    ret
150  %c = mul i32 %a, 20
151  %d = add i32 %c, %b
152  ret i32 %d
153}
154
155define i32 @addmul24(i32 %a, i32 %b) {
156; RV32I-LABEL: addmul24:
157; RV32I:       # %bb.0:
158; RV32I-NEXT:    slli a2, a0, 3
159; RV32I-NEXT:    slli a0, a0, 5
160; RV32I-NEXT:    sub a0, a0, a2
161; RV32I-NEXT:    add a0, a0, a1
162; RV32I-NEXT:    ret
163;
164; RV32ZBA-LABEL: addmul24:
165; RV32ZBA:       # %bb.0:
166; RV32ZBA-NEXT:    sh1add a0, a0, a0
167; RV32ZBA-NEXT:    sh3add a0, a0, a1
168; RV32ZBA-NEXT:    ret
169  %c = mul i32 %a, 24
170  %d = add i32 %c, %b
171  ret i32 %d
172}
173
174define i32 @addmul36(i32 %a, i32 %b) {
175; RV32I-LABEL: addmul36:
176; RV32I:       # %bb.0:
177; RV32I-NEXT:    li a2, 36
178; RV32I-NEXT:    mul a0, a0, a2
179; RV32I-NEXT:    add a0, a0, a1
180; RV32I-NEXT:    ret
181;
182; RV32ZBA-LABEL: addmul36:
183; RV32ZBA:       # %bb.0:
184; RV32ZBA-NEXT:    sh3add a0, a0, a0
185; RV32ZBA-NEXT:    sh2add a0, a0, a1
186; RV32ZBA-NEXT:    ret
187  %c = mul i32 %a, 36
188  %d = add i32 %c, %b
189  ret i32 %d
190}
191
192define i32 @addmul40(i32 %a, i32 %b) {
193; RV32I-LABEL: addmul40:
194; RV32I:       # %bb.0:
195; RV32I-NEXT:    li a2, 40
196; RV32I-NEXT:    mul a0, a0, a2
197; RV32I-NEXT:    add a0, a0, a1
198; RV32I-NEXT:    ret
199;
200; RV32ZBA-LABEL: addmul40:
201; RV32ZBA:       # %bb.0:
202; RV32ZBA-NEXT:    sh2add a0, a0, a0
203; RV32ZBA-NEXT:    sh3add a0, a0, a1
204; RV32ZBA-NEXT:    ret
205  %c = mul i32 %a, 40
206  %d = add i32 %c, %b
207  ret i32 %d
208}
209
210define i32 @addmul72(i32 %a, i32 %b) {
211; RV32I-LABEL: addmul72:
212; RV32I:       # %bb.0:
213; RV32I-NEXT:    li a2, 72
214; RV32I-NEXT:    mul a0, a0, a2
215; RV32I-NEXT:    add a0, a0, a1
216; RV32I-NEXT:    ret
217;
218; RV32ZBA-LABEL: addmul72:
219; RV32ZBA:       # %bb.0:
220; RV32ZBA-NEXT:    sh3add a0, a0, a0
221; RV32ZBA-NEXT:    sh3add a0, a0, a1
222; RV32ZBA-NEXT:    ret
223  %c = mul i32 %a, 72
224  %d = add i32 %c, %b
225  ret i32 %d
226}
227
228define i32 @mul96(i32 %a) {
229; RV32I-LABEL: mul96:
230; RV32I:       # %bb.0:
231; RV32I-NEXT:    slli a1, a0, 5
232; RV32I-NEXT:    slli a0, a0, 7
233; RV32I-NEXT:    sub a0, a0, a1
234; RV32I-NEXT:    ret
235;
236; RV32ZBA-LABEL: mul96:
237; RV32ZBA:       # %bb.0:
238; RV32ZBA-NEXT:    sh1add a0, a0, a0
239; RV32ZBA-NEXT:    slli a0, a0, 5
240; RV32ZBA-NEXT:    ret
241  %c = mul i32 %a, 96
242  ret i32 %c
243}
244
245define i32 @mul160(i32 %a) {
246; RV32I-LABEL: mul160:
247; RV32I:       # %bb.0:
248; RV32I-NEXT:    li a1, 160
249; RV32I-NEXT:    mul a0, a0, a1
250; RV32I-NEXT:    ret
251;
252; RV32ZBA-LABEL: mul160:
253; RV32ZBA:       # %bb.0:
254; RV32ZBA-NEXT:    sh2add a0, a0, a0
255; RV32ZBA-NEXT:    slli a0, a0, 5
256; RV32ZBA-NEXT:    ret
257  %c = mul i32 %a, 160
258  ret i32 %c
259}
260
261define i32 @mul288(i32 %a) {
262; RV32I-LABEL: mul288:
263; RV32I:       # %bb.0:
264; RV32I-NEXT:    li a1, 288
265; RV32I-NEXT:    mul a0, a0, a1
266; RV32I-NEXT:    ret
267;
268; RV32ZBA-LABEL: mul288:
269; RV32ZBA:       # %bb.0:
270; RV32ZBA-NEXT:    sh3add a0, a0, a0
271; RV32ZBA-NEXT:    slli a0, a0, 5
272; RV32ZBA-NEXT:    ret
273  %c = mul i32 %a, 288
274  ret i32 %c
275}
276
277define i32 @mul258(i32 %a) {
278; RV32I-LABEL: mul258:
279; RV32I:       # %bb.0:
280; RV32I-NEXT:    li a1, 258
281; RV32I-NEXT:    mul a0, a0, a1
282; RV32I-NEXT:    ret
283;
284; RV32ZBA-LABEL: mul258:
285; RV32ZBA:       # %bb.0:
286; RV32ZBA-NEXT:    slli a1, a0, 8
287; RV32ZBA-NEXT:    sh1add a0, a0, a1
288; RV32ZBA-NEXT:    ret
289  %c = mul i32 %a, 258
290  ret i32 %c
291}
292
293define i32 @mul260(i32 %a) {
294; RV32I-LABEL: mul260:
295; RV32I:       # %bb.0:
296; RV32I-NEXT:    li a1, 260
297; RV32I-NEXT:    mul a0, a0, a1
298; RV32I-NEXT:    ret
299;
300; RV32ZBA-LABEL: mul260:
301; RV32ZBA:       # %bb.0:
302; RV32ZBA-NEXT:    slli a1, a0, 8
303; RV32ZBA-NEXT:    sh2add a0, a0, a1
304; RV32ZBA-NEXT:    ret
305  %c = mul i32 %a, 260
306  ret i32 %c
307}
308
309define i32 @mul264(i32 %a) {
310; RV32I-LABEL: mul264:
311; RV32I:       # %bb.0:
312; RV32I-NEXT:    li a1, 264
313; RV32I-NEXT:    mul a0, a0, a1
314; RV32I-NEXT:    ret
315;
316; RV32ZBA-LABEL: mul264:
317; RV32ZBA:       # %bb.0:
318; RV32ZBA-NEXT:    slli a1, a0, 8
319; RV32ZBA-NEXT:    sh3add a0, a0, a1
320; RV32ZBA-NEXT:    ret
321  %c = mul i32 %a, 264
322  ret i32 %c
323}
324
325define i32 @mul11(i32 %a) {
326; RV32I-LABEL: mul11:
327; RV32I:       # %bb.0:
328; RV32I-NEXT:    li a1, 11
329; RV32I-NEXT:    mul a0, a0, a1
330; RV32I-NEXT:    ret
331;
332; RV32ZBA-LABEL: mul11:
333; RV32ZBA:       # %bb.0:
334; RV32ZBA-NEXT:    sh2add a1, a0, a0
335; RV32ZBA-NEXT:    sh1add a0, a1, a0
336; RV32ZBA-NEXT:    ret
337  %c = mul i32 %a, 11
338  ret i32 %c
339}
340
341define i32 @mul19(i32 %a) {
342; RV32I-LABEL: mul19:
343; RV32I:       # %bb.0:
344; RV32I-NEXT:    li a1, 19
345; RV32I-NEXT:    mul a0, a0, a1
346; RV32I-NEXT:    ret
347;
348; RV32ZBA-LABEL: mul19:
349; RV32ZBA:       # %bb.0:
350; RV32ZBA-NEXT:    sh3add a1, a0, a0
351; RV32ZBA-NEXT:    sh1add a0, a1, a0
352; RV32ZBA-NEXT:    ret
353  %c = mul i32 %a, 19
354  ret i32 %c
355}
356
357define i32 @mul13(i32 %a) {
358; RV32I-LABEL: mul13:
359; RV32I:       # %bb.0:
360; RV32I-NEXT:    li a1, 13
361; RV32I-NEXT:    mul a0, a0, a1
362; RV32I-NEXT:    ret
363;
364; RV32ZBA-LABEL: mul13:
365; RV32ZBA:       # %bb.0:
366; RV32ZBA-NEXT:    sh1add a1, a0, a0
367; RV32ZBA-NEXT:    sh2add a0, a1, a0
368; RV32ZBA-NEXT:    ret
369  %c = mul i32 %a, 13
370  ret i32 %c
371}
372
373define i32 @mul21(i32 %a) {
374; RV32I-LABEL: mul21:
375; RV32I:       # %bb.0:
376; RV32I-NEXT:    li a1, 21
377; RV32I-NEXT:    mul a0, a0, a1
378; RV32I-NEXT:    ret
379;
380; RV32ZBA-LABEL: mul21:
381; RV32ZBA:       # %bb.0:
382; RV32ZBA-NEXT:    sh2add a1, a0, a0
383; RV32ZBA-NEXT:    sh2add a0, a1, a0
384; RV32ZBA-NEXT:    ret
385  %c = mul i32 %a, 21
386  ret i32 %c
387}
388
389define i32 @mul37(i32 %a) {
390; RV32I-LABEL: mul37:
391; RV32I:       # %bb.0:
392; RV32I-NEXT:    li a1, 37
393; RV32I-NEXT:    mul a0, a0, a1
394; RV32I-NEXT:    ret
395;
396; RV32ZBA-LABEL: mul37:
397; RV32ZBA:       # %bb.0:
398; RV32ZBA-NEXT:    sh3add a1, a0, a0
399; RV32ZBA-NEXT:    sh2add a0, a1, a0
400; RV32ZBA-NEXT:    ret
401  %c = mul i32 %a, 37
402  ret i32 %c
403}
404
405define i32 @mul25(i32 %a) {
406; RV32I-LABEL: mul25:
407; RV32I:       # %bb.0:
408; RV32I-NEXT:    li a1, 25
409; RV32I-NEXT:    mul a0, a0, a1
410; RV32I-NEXT:    ret
411;
412; RV32ZBA-LABEL: mul25:
413; RV32ZBA:       # %bb.0:
414; RV32ZBA-NEXT:    sh2add a0, a0, a0
415; RV32ZBA-NEXT:    sh2add a0, a0, a0
416; RV32ZBA-NEXT:    ret
417  %c = mul i32 %a, 25
418  ret i32 %c
419}
420
421define i32 @mul41(i32 %a) {
422; RV32I-LABEL: mul41:
423; RV32I:       # %bb.0:
424; RV32I-NEXT:    li a1, 41
425; RV32I-NEXT:    mul a0, a0, a1
426; RV32I-NEXT:    ret
427;
428; RV32ZBA-LABEL: mul41:
429; RV32ZBA:       # %bb.0:
430; RV32ZBA-NEXT:    sh2add a1, a0, a0
431; RV32ZBA-NEXT:    sh3add a0, a1, a0
432; RV32ZBA-NEXT:    ret
433  %c = mul i32 %a, 41
434  ret i32 %c
435}
436
437define i32 @mul73(i32 %a) {
438; RV32I-LABEL: mul73:
439; RV32I:       # %bb.0:
440; RV32I-NEXT:    li a1, 73
441; RV32I-NEXT:    mul a0, a0, a1
442; RV32I-NEXT:    ret
443;
444; RV32ZBA-LABEL: mul73:
445; RV32ZBA:       # %bb.0:
446; RV32ZBA-NEXT:    sh3add a1, a0, a0
447; RV32ZBA-NEXT:    sh3add a0, a1, a0
448; RV32ZBA-NEXT:    ret
449  %c = mul i32 %a, 73
450  ret i32 %c
451}
452
453define i32 @mul27(i32 %a) {
454; RV32I-LABEL: mul27:
455; RV32I:       # %bb.0:
456; RV32I-NEXT:    li a1, 27
457; RV32I-NEXT:    mul a0, a0, a1
458; RV32I-NEXT:    ret
459;
460; RV32ZBA-LABEL: mul27:
461; RV32ZBA:       # %bb.0:
462; RV32ZBA-NEXT:    sh1add a0, a0, a0
463; RV32ZBA-NEXT:    sh3add a0, a0, a0
464; RV32ZBA-NEXT:    ret
465  %c = mul i32 %a, 27
466  ret i32 %c
467}
468
469define i32 @mul45(i32 %a) {
470; RV32I-LABEL: mul45:
471; RV32I:       # %bb.0:
472; RV32I-NEXT:    li a1, 45
473; RV32I-NEXT:    mul a0, a0, a1
474; RV32I-NEXT:    ret
475;
476; RV32ZBA-LABEL: mul45:
477; RV32ZBA:       # %bb.0:
478; RV32ZBA-NEXT:    sh2add a0, a0, a0
479; RV32ZBA-NEXT:    sh3add a0, a0, a0
480; RV32ZBA-NEXT:    ret
481  %c = mul i32 %a, 45
482  ret i32 %c
483}
484
485define i32 @mul81(i32 %a) {
486; RV32I-LABEL: mul81:
487; RV32I:       # %bb.0:
488; RV32I-NEXT:    li a1, 81
489; RV32I-NEXT:    mul a0, a0, a1
490; RV32I-NEXT:    ret
491;
492; RV32ZBA-LABEL: mul81:
493; RV32ZBA:       # %bb.0:
494; RV32ZBA-NEXT:    sh3add a0, a0, a0
495; RV32ZBA-NEXT:    sh3add a0, a0, a0
496; RV32ZBA-NEXT:    ret
497  %c = mul i32 %a, 81
498  ret i32 %c
499}
500
501define i32 @mul4098(i32 %a) {
502; RV32I-LABEL: mul4098:
503; RV32I:       # %bb.0:
504; RV32I-NEXT:    slli a1, a0, 1
505; RV32I-NEXT:    slli a0, a0, 12
506; RV32I-NEXT:    add a0, a0, a1
507; RV32I-NEXT:    ret
508;
509; RV32ZBA-LABEL: mul4098:
510; RV32ZBA:       # %bb.0:
511; RV32ZBA-NEXT:    slli a1, a0, 12
512; RV32ZBA-NEXT:    sh1add a0, a0, a1
513; RV32ZBA-NEXT:    ret
514  %c = mul i32 %a, 4098
515  ret i32 %c
516}
517
518define i32 @mul4100(i32 %a) {
519; RV32I-LABEL: mul4100:
520; RV32I:       # %bb.0:
521; RV32I-NEXT:    slli a1, a0, 2
522; RV32I-NEXT:    slli a0, a0, 12
523; RV32I-NEXT:    add a0, a0, a1
524; RV32I-NEXT:    ret
525;
526; RV32ZBA-LABEL: mul4100:
527; RV32ZBA:       # %bb.0:
528; RV32ZBA-NEXT:    slli a1, a0, 12
529; RV32ZBA-NEXT:    sh2add a0, a0, a1
530; RV32ZBA-NEXT:    ret
531  %c = mul i32 %a, 4100
532  ret i32 %c
533}
534
535define i32 @mul4104(i32 %a) {
536; RV32I-LABEL: mul4104:
537; RV32I:       # %bb.0:
538; RV32I-NEXT:    slli a1, a0, 3
539; RV32I-NEXT:    slli a0, a0, 12
540; RV32I-NEXT:    add a0, a0, a1
541; RV32I-NEXT:    ret
542;
543; RV32ZBA-LABEL: mul4104:
544; RV32ZBA:       # %bb.0:
545; RV32ZBA-NEXT:    slli a1, a0, 12
546; RV32ZBA-NEXT:    sh3add a0, a0, a1
547; RV32ZBA-NEXT:    ret
548  %c = mul i32 %a, 4104
549  ret i32 %c
550}
551
552define i32 @add4104(i32 %a) {
553; RV32I-LABEL: add4104:
554; RV32I:       # %bb.0:
555; RV32I-NEXT:    lui a1, 1
556; RV32I-NEXT:    addi a1, a1, 8
557; RV32I-NEXT:    add a0, a0, a1
558; RV32I-NEXT:    ret
559;
560; RV32ZBA-LABEL: add4104:
561; RV32ZBA:       # %bb.0:
562; RV32ZBA-NEXT:    li a1, 1026
563; RV32ZBA-NEXT:    sh2add a0, a1, a0
564; RV32ZBA-NEXT:    ret
565  %c = add i32 %a, 4104
566  ret i32 %c
567}
568
569define i32 @add8208(i32 %a) {
570; RV32I-LABEL: add8208:
571; RV32I:       # %bb.0:
572; RV32I-NEXT:    lui a1, 2
573; RV32I-NEXT:    addi a1, a1, 16
574; RV32I-NEXT:    add a0, a0, a1
575; RV32I-NEXT:    ret
576;
577; RV32ZBA-LABEL: add8208:
578; RV32ZBA:       # %bb.0:
579; RV32ZBA-NEXT:    li a1, 1026
580; RV32ZBA-NEXT:    sh3add a0, a1, a0
581; RV32ZBA-NEXT:    ret
582  %c = add i32 %a, 8208
583  ret i32 %c
584}
585
586define i32 @add8192(i32 %a) {
587; CHECK-LABEL: add8192:
588; CHECK:       # %bb.0:
589; CHECK-NEXT:    lui a1, 2
590; CHECK-NEXT:    add a0, a0, a1
591; CHECK-NEXT:    ret
592  %c = add i32 %a, 8192
593  ret i32 %c
594}
595
596define i32 @addshl_5_6(i32 %a, i32 %b) {
597; RV32I-LABEL: addshl_5_6:
598; RV32I:       # %bb.0:
599; RV32I-NEXT:    slli a0, a0, 5
600; RV32I-NEXT:    slli a1, a1, 6
601; RV32I-NEXT:    add a0, a0, a1
602; RV32I-NEXT:    ret
603;
604; RV32ZBA-LABEL: addshl_5_6:
605; RV32ZBA:       # %bb.0:
606; RV32ZBA-NEXT:    sh1add a0, a1, a0
607; RV32ZBA-NEXT:    slli a0, a0, 5
608; RV32ZBA-NEXT:    ret
609  %c = shl i32 %a, 5
610  %d = shl i32 %b, 6
611  %e = add i32 %c, %d
612  ret i32 %e
613}
614
615define i32 @addshl_5_7(i32 %a, i32 %b) {
616; RV32I-LABEL: addshl_5_7:
617; RV32I:       # %bb.0:
618; RV32I-NEXT:    slli a0, a0, 5
619; RV32I-NEXT:    slli a1, a1, 7
620; RV32I-NEXT:    add a0, a0, a1
621; RV32I-NEXT:    ret
622;
623; RV32ZBA-LABEL: addshl_5_7:
624; RV32ZBA:       # %bb.0:
625; RV32ZBA-NEXT:    sh2add a0, a1, a0
626; RV32ZBA-NEXT:    slli a0, a0, 5
627; RV32ZBA-NEXT:    ret
628  %c = shl i32 %a, 5
629  %d = shl i32 %b, 7
630  %e = add i32 %c, %d
631  ret i32 %e
632}
633
634define i32 @addshl_5_8(i32 %a, i32 %b) {
635; RV32I-LABEL: addshl_5_8:
636; RV32I:       # %bb.0:
637; RV32I-NEXT:    slli a0, a0, 5
638; RV32I-NEXT:    slli a1, a1, 8
639; RV32I-NEXT:    add a0, a0, a1
640; RV32I-NEXT:    ret
641;
642; RV32ZBA-LABEL: addshl_5_8:
643; RV32ZBA:       # %bb.0:
644; RV32ZBA-NEXT:    sh3add a0, a1, a0
645; RV32ZBA-NEXT:    slli a0, a0, 5
646; RV32ZBA-NEXT:    ret
647  %c = shl i32 %a, 5
648  %d = shl i32 %b, 8
649  %e = add i32 %c, %d
650  ret i32 %e
651}
652
653define i32 @srli_1_sh2add(ptr %0, i32 %1) {
654; RV32I-LABEL: srli_1_sh2add:
655; RV32I:       # %bb.0:
656; RV32I-NEXT:    slli a1, a1, 1
657; RV32I-NEXT:    andi a1, a1, -4
658; RV32I-NEXT:    add a0, a0, a1
659; RV32I-NEXT:    lw a0, 0(a0)
660; RV32I-NEXT:    ret
661;
662; RV32ZBA-LABEL: srli_1_sh2add:
663; RV32ZBA:       # %bb.0:
664; RV32ZBA-NEXT:    srli a1, a1, 1
665; RV32ZBA-NEXT:    sh2add a0, a1, a0
666; RV32ZBA-NEXT:    lw a0, 0(a0)
667; RV32ZBA-NEXT:    ret
668  %3 = lshr i32 %1, 1
669  %4 = getelementptr inbounds i32, ptr %0, i32 %3
670  %5 = load i32, ptr %4, align 4
671  ret i32 %5
672}
673
674define i64 @srli_2_sh3add(ptr %0, i32 %1) {
675; RV32I-LABEL: srli_2_sh3add:
676; RV32I:       # %bb.0:
677; RV32I-NEXT:    slli a1, a1, 1
678; RV32I-NEXT:    andi a1, a1, -8
679; RV32I-NEXT:    add a1, a0, a1
680; RV32I-NEXT:    lw a0, 0(a1)
681; RV32I-NEXT:    lw a1, 4(a1)
682; RV32I-NEXT:    ret
683;
684; RV32ZBA-LABEL: srli_2_sh3add:
685; RV32ZBA:       # %bb.0:
686; RV32ZBA-NEXT:    srli a1, a1, 2
687; RV32ZBA-NEXT:    sh3add a1, a1, a0
688; RV32ZBA-NEXT:    lw a0, 0(a1)
689; RV32ZBA-NEXT:    lw a1, 4(a1)
690; RV32ZBA-NEXT:    ret
691  %3 = lshr i32 %1, 2
692  %4 = getelementptr inbounds i64, ptr %0, i32 %3
693  %5 = load i64, ptr %4, align 8
694  ret i64 %5
695}
696
697define signext i16 @srli_2_sh1add(ptr %0, i32 %1) {
698; RV32I-LABEL: srli_2_sh1add:
699; RV32I:       # %bb.0:
700; RV32I-NEXT:    srli a1, a1, 1
701; RV32I-NEXT:    andi a1, a1, -2
702; RV32I-NEXT:    add a0, a0, a1
703; RV32I-NEXT:    lh a0, 0(a0)
704; RV32I-NEXT:    ret
705;
706; RV32ZBA-LABEL: srli_2_sh1add:
707; RV32ZBA:       # %bb.0:
708; RV32ZBA-NEXT:    srli a1, a1, 2
709; RV32ZBA-NEXT:    sh1add a0, a1, a0
710; RV32ZBA-NEXT:    lh a0, 0(a0)
711; RV32ZBA-NEXT:    ret
712  %3 = lshr i32 %1, 2
713  %4 = getelementptr inbounds i16, ptr %0, i32 %3
714  %5 = load i16, ptr %4, align 2
715  ret i16 %5
716}
717
718define i32 @srli_3_sh2add(ptr %0, i32 %1) {
719; RV32I-LABEL: srli_3_sh2add:
720; RV32I:       # %bb.0:
721; RV32I-NEXT:    srli a1, a1, 1
722; RV32I-NEXT:    andi a1, a1, -4
723; RV32I-NEXT:    add a0, a0, a1
724; RV32I-NEXT:    lw a0, 0(a0)
725; RV32I-NEXT:    ret
726;
727; RV32ZBA-LABEL: srli_3_sh2add:
728; RV32ZBA:       # %bb.0:
729; RV32ZBA-NEXT:    srli a1, a1, 3
730; RV32ZBA-NEXT:    sh2add a0, a1, a0
731; RV32ZBA-NEXT:    lw a0, 0(a0)
732; RV32ZBA-NEXT:    ret
733  %3 = lshr i32 %1, 3
734  %4 = getelementptr inbounds i32, ptr %0, i32 %3
735  %5 = load i32, ptr %4, align 4
736  ret i32 %5
737}
738
739define i64 @srli_4_sh3add(ptr %0, i32 %1) {
740; RV32I-LABEL: srli_4_sh3add:
741; RV32I:       # %bb.0:
742; RV32I-NEXT:    srli a1, a1, 1
743; RV32I-NEXT:    andi a1, a1, -8
744; RV32I-NEXT:    add a1, a0, a1
745; RV32I-NEXT:    lw a0, 0(a1)
746; RV32I-NEXT:    lw a1, 4(a1)
747; RV32I-NEXT:    ret
748;
749; RV32ZBA-LABEL: srli_4_sh3add:
750; RV32ZBA:       # %bb.0:
751; RV32ZBA-NEXT:    srli a1, a1, 4
752; RV32ZBA-NEXT:    sh3add a1, a1, a0
753; RV32ZBA-NEXT:    lw a0, 0(a1)
754; RV32ZBA-NEXT:    lw a1, 4(a1)
755; RV32ZBA-NEXT:    ret
756  %3 = lshr i32 %1, 4
757  %4 = getelementptr inbounds i64, ptr %0, i32 %3
758  %5 = load i64, ptr %4, align 8
759  ret i64 %5
760}
761
762define i32 @mul_neg1(i32 %a) {
763; CHECK-LABEL: mul_neg1:
764; CHECK:       # %bb.0:
765; CHECK-NEXT:    neg a0, a0
766; CHECK-NEXT:    ret
767  %c = mul i32 %a, -1
768  ret i32 %c
769}
770
771define i32 @mul_neg2(i32 %a) {
772; CHECK-LABEL: mul_neg2:
773; CHECK:       # %bb.0:
774; CHECK-NEXT:    slli a0, a0, 1
775; CHECK-NEXT:    neg a0, a0
776; CHECK-NEXT:    ret
777  %c = mul i32 %a, -2
778  ret i32 %c
779}
780
781define i32 @mul_neg3(i32 %a) {
782; RV32I-LABEL: mul_neg3:
783; RV32I:       # %bb.0:
784; RV32I-NEXT:    slli a1, a0, 1
785; RV32I-NEXT:    neg a0, a0
786; RV32I-NEXT:    sub a0, a0, a1
787; RV32I-NEXT:    ret
788;
789; RV32ZBA-LABEL: mul_neg3:
790; RV32ZBA:       # %bb.0:
791; RV32ZBA-NEXT:    sh1add a0, a0, a0
792; RV32ZBA-NEXT:    neg a0, a0
793; RV32ZBA-NEXT:    ret
794  %c = mul i32 %a, -3
795  ret i32 %c
796}
797
798define i32 @mul_neg4(i32 %a) {
799; CHECK-LABEL: mul_neg4:
800; CHECK:       # %bb.0:
801; CHECK-NEXT:    slli a0, a0, 2
802; CHECK-NEXT:    neg a0, a0
803; CHECK-NEXT:    ret
804  %c = mul i32 %a, -4
805  ret i32 %c
806}
807
808define i32 @mul_neg5(i32 %a) {
809; RV32I-LABEL: mul_neg5:
810; RV32I:       # %bb.0:
811; RV32I-NEXT:    slli a1, a0, 2
812; RV32I-NEXT:    neg a0, a0
813; RV32I-NEXT:    sub a0, a0, a1
814; RV32I-NEXT:    ret
815;
816; RV32ZBA-LABEL: mul_neg5:
817; RV32ZBA:       # %bb.0:
818; RV32ZBA-NEXT:    sh2add a0, a0, a0
819; RV32ZBA-NEXT:    neg a0, a0
820; RV32ZBA-NEXT:    ret
821  %c = mul i32 %a, -5
822  ret i32 %c
823}
824
825define i32 @mul_neg6(i32 %a) {
826; CHECK-LABEL: mul_neg6:
827; CHECK:       # %bb.0:
828; CHECK-NEXT:    li a1, -6
829; CHECK-NEXT:    mul a0, a0, a1
830; CHECK-NEXT:    ret
831  %c = mul i32 %a, -6
832  ret i32 %c
833}
834
835define i32 @mul_neg7(i32 %a) {
836; CHECK-LABEL: mul_neg7:
837; CHECK:       # %bb.0:
838; CHECK-NEXT:    slli a1, a0, 3
839; CHECK-NEXT:    sub a0, a0, a1
840; CHECK-NEXT:    ret
841  %c = mul i32 %a, -7
842  ret i32 %c
843}
844
845define i32 @mul_neg8(i32 %a) {
846; CHECK-LABEL: mul_neg8:
847; CHECK:       # %bb.0:
848; CHECK-NEXT:    slli a0, a0, 3
849; CHECK-NEXT:    neg a0, a0
850; CHECK-NEXT:    ret
851  %c = mul i32 %a, -8
852  ret i32 %c
853}
854