1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefixes=RV32I 4; RUN: llc -mtriple=riscv32 -mattr=+xtheadbs -verify-machineinstrs < %s \ 5; RUN: | FileCheck %s -check-prefixes=RV32XTHEADBS 6 7define i32 @th_tst_i32(i32 %a) nounwind { 8; RV32I-LABEL: th_tst_i32: 9; RV32I: # %bb.0: 10; RV32I-NEXT: slli a0, a0, 26 11; RV32I-NEXT: srli a0, a0, 31 12; RV32I-NEXT: ret 13; 14; RV32XTHEADBS-LABEL: th_tst_i32: 15; RV32XTHEADBS: # %bb.0: 16; RV32XTHEADBS-NEXT: th.tst a0, a0, 5 17; RV32XTHEADBS-NEXT: ret 18 %shr = lshr i32 %a, 5 19 %and = and i32 %shr, 1 20 ret i32 %and 21} 22 23define i64 @th_tst_i64(i64 %a) nounwind { 24; RV32I-LABEL: th_tst_i64: 25; RV32I: # %bb.0: 26; RV32I-NEXT: slli a0, a0, 26 27; RV32I-NEXT: srli a0, a0, 31 28; RV32I-NEXT: li a1, 0 29; RV32I-NEXT: ret 30; 31; RV32XTHEADBS-LABEL: th_tst_i64: 32; RV32XTHEADBS: # %bb.0: 33; RV32XTHEADBS-NEXT: th.tst a0, a0, 5 34; RV32XTHEADBS-NEXT: li a1, 0 35; RV32XTHEADBS-NEXT: ret 36 %shr = lshr i64 %a, 5 37 %and = and i64 %shr, 1 38 ret i64 %and 39} 40 41define signext i32 @th_tst_i32_cmp(i32 signext %a) nounwind { 42; RV32I-LABEL: th_tst_i32_cmp: 43; RV32I: # %bb.0: 44; RV32I-NEXT: slli a0, a0, 26 45; RV32I-NEXT: srli a0, a0, 31 46; RV32I-NEXT: ret 47; 48; RV32XTHEADBS-LABEL: th_tst_i32_cmp: 49; RV32XTHEADBS: # %bb.0: 50; RV32XTHEADBS-NEXT: th.tst a0, a0, 5 51; RV32XTHEADBS-NEXT: ret 52 %and = and i32 %a, 32 53 %cmp = icmp ne i32 %and, 0 54 %zext = zext i1 %cmp to i32 55 ret i32 %zext 56} 57 58define i64 @th_tst_i64_cmp(i64 %a) nounwind { 59; RV32I-LABEL: th_tst_i64_cmp: 60; RV32I: # %bb.0: 61; RV32I-NEXT: slli a0, a0, 26 62; RV32I-NEXT: srli a0, a0, 31 63; RV32I-NEXT: li a1, 0 64; RV32I-NEXT: ret 65; 66; RV32XTHEADBS-LABEL: th_tst_i64_cmp: 67; RV32XTHEADBS: # %bb.0: 68; RV32XTHEADBS-NEXT: th.tst a0, a0, 5 69; RV32XTHEADBS-NEXT: li a1, 0 70; RV32XTHEADBS-NEXT: ret 71 %and = and i64 %a, 32 72 %cmp = icmp ne i64 %and, 0 73 %zext = zext i1 %cmp to i64 74 ret i64 %zext 75} 76