1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --extra_scrub 2; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I 4; RUN: llc -mtriple=riscv32 -mattr=+m,+xtheadba -verify-machineinstrs < %s \ 5; RUN: | FileCheck %s -check-prefixes=CHECK,RV32XTHEADBA 6 7define signext i16 @th_addsl_1(i64 %0, ptr %1) { 8; RV32I-LABEL: th_addsl_1: 9; RV32I: # %bb.0: 10; RV32I-NEXT: slli a0, a0, 1 11; RV32I-NEXT: add a0, a2, a0 12; RV32I-NEXT: lh a0, 0(a0) 13; RV32I-NEXT: ret 14; 15; RV32XTHEADBA-LABEL: th_addsl_1: 16; RV32XTHEADBA: # %bb.0: 17; RV32XTHEADBA-NEXT: th.addsl a0, a2, a0, 1 18; RV32XTHEADBA-NEXT: lh a0, 0(a0) 19; RV32XTHEADBA-NEXT: ret 20 %3 = getelementptr inbounds i16, ptr %1, i64 %0 21 %4 = load i16, ptr %3 22 ret i16 %4 23} 24 25define signext i32 @th_addsl_2(i64 %0, ptr %1) { 26; RV32I-LABEL: th_addsl_2: 27; RV32I: # %bb.0: 28; RV32I-NEXT: slli a0, a0, 2 29; RV32I-NEXT: add a0, a2, a0 30; RV32I-NEXT: lw a0, 0(a0) 31; RV32I-NEXT: ret 32; 33; RV32XTHEADBA-LABEL: th_addsl_2: 34; RV32XTHEADBA: # %bb.0: 35; RV32XTHEADBA-NEXT: th.addsl a0, a2, a0, 2 36; RV32XTHEADBA-NEXT: lw a0, 0(a0) 37; RV32XTHEADBA-NEXT: ret 38 %3 = getelementptr inbounds i32, ptr %1, i64 %0 39 %4 = load i32, ptr %3 40 ret i32 %4 41} 42 43define i64 @th_addsl_3(i64 %0, ptr %1) { 44; RV32I-LABEL: th_addsl_3: 45; RV32I: # %bb.0: 46; RV32I-NEXT: slli a0, a0, 3 47; RV32I-NEXT: add a2, a2, a0 48; RV32I-NEXT: lw a0, 0(a2) 49; RV32I-NEXT: lw a1, 4(a2) 50; RV32I-NEXT: ret 51; 52; RV32XTHEADBA-LABEL: th_addsl_3: 53; RV32XTHEADBA: # %bb.0: 54; RV32XTHEADBA-NEXT: th.addsl a1, a2, a0, 3 55; RV32XTHEADBA-NEXT: lw a0, 0(a1) 56; RV32XTHEADBA-NEXT: lw a1, 4(a1) 57; RV32XTHEADBA-NEXT: ret 58 %3 = getelementptr inbounds i64, ptr %1, i64 %0 59 %4 = load i64, ptr %3 60 ret i64 %4 61} 62 63; Type legalization inserts a sext_inreg after the first add. That add will be 64; selected as th.addsl which does not sign extend. SimplifyDemandedBits is unable 65; to remove the sext_inreg because it has multiple uses. The ashr will use the 66; sext_inreg to become sraiw. This leaves the sext_inreg only used by the shl. 67; If the shl is selected as sllw, we don't need the sext_inreg. 68define i64 @th_addsl_2_extra_sext(i32 %x, i32 %y, i32 %z) { 69; RV32I-LABEL: th_addsl_2_extra_sext: 70; RV32I: # %bb.0: 71; RV32I-NEXT: slli a0, a0, 2 72; RV32I-NEXT: add a0, a0, a1 73; RV32I-NEXT: sll a1, a2, a0 74; RV32I-NEXT: srai a2, a0, 2 75; RV32I-NEXT: mul a0, a1, a2 76; RV32I-NEXT: mulh a1, a1, a2 77; RV32I-NEXT: ret 78; 79; RV32XTHEADBA-LABEL: th_addsl_2_extra_sext: 80; RV32XTHEADBA: # %bb.0: 81; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 2 82; RV32XTHEADBA-NEXT: sll a1, a2, a0 83; RV32XTHEADBA-NEXT: srai a2, a0, 2 84; RV32XTHEADBA-NEXT: mul a0, a1, a2 85; RV32XTHEADBA-NEXT: mulh a1, a1, a2 86; RV32XTHEADBA-NEXT: ret 87 %a = shl i32 %x, 2 88 %b = add i32 %a, %y 89 %c = shl i32 %z, %b 90 %d = ashr i32 %b, 2 91 %e = sext i32 %c to i64 92 %f = sext i32 %d to i64 93 %g = mul i64 %e, %f 94 ret i64 %g 95} 96 97define i32 @addmul6(i32 %a, i32 %b) { 98; RV32I-LABEL: addmul6: 99; RV32I: # %bb.0: 100; RV32I-NEXT: slli a2, a0, 1 101; RV32I-NEXT: slli a0, a0, 3 102; RV32I-NEXT: sub a0, a0, a2 103; RV32I-NEXT: add a0, a0, a1 104; RV32I-NEXT: ret 105; 106; RV32XTHEADBA-LABEL: addmul6: 107; RV32XTHEADBA: # %bb.0: 108; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 1 109; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 1 110; RV32XTHEADBA-NEXT: ret 111 %c = mul i32 %a, 6 112 %d = add i32 %c, %b 113 ret i32 %d 114} 115 116define i32 @addmul10(i32 %a, i32 %b) { 117; RV32I-LABEL: addmul10: 118; RV32I: # %bb.0: 119; RV32I-NEXT: li a2, 10 120; RV32I-NEXT: mul a0, a0, a2 121; RV32I-NEXT: add a0, a0, a1 122; RV32I-NEXT: ret 123; 124; RV32XTHEADBA-LABEL: addmul10: 125; RV32XTHEADBA: # %bb.0: 126; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 2 127; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 1 128; RV32XTHEADBA-NEXT: ret 129 %c = mul i32 %a, 10 130 %d = add i32 %c, %b 131 ret i32 %d 132} 133 134define i32 @addmul12(i32 %a, i32 %b) { 135; RV32I-LABEL: addmul12: 136; RV32I: # %bb.0: 137; RV32I-NEXT: slli a2, a0, 2 138; RV32I-NEXT: slli a0, a0, 4 139; RV32I-NEXT: sub a0, a0, a2 140; RV32I-NEXT: add a0, a0, a1 141; RV32I-NEXT: ret 142; 143; RV32XTHEADBA-LABEL: addmul12: 144; RV32XTHEADBA: # %bb.0: 145; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 1 146; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 2 147; RV32XTHEADBA-NEXT: ret 148 %c = mul i32 %a, 12 149 %d = add i32 %c, %b 150 ret i32 %d 151} 152 153define i32 @addmul18(i32 %a, i32 %b) { 154; RV32I-LABEL: addmul18: 155; RV32I: # %bb.0: 156; RV32I-NEXT: li a2, 18 157; RV32I-NEXT: mul a0, a0, a2 158; RV32I-NEXT: add a0, a0, a1 159; RV32I-NEXT: ret 160; 161; RV32XTHEADBA-LABEL: addmul18: 162; RV32XTHEADBA: # %bb.0: 163; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 3 164; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 1 165; RV32XTHEADBA-NEXT: ret 166 %c = mul i32 %a, 18 167 %d = add i32 %c, %b 168 ret i32 %d 169} 170 171define i32 @addmul20(i32 %a, i32 %b) { 172; RV32I-LABEL: addmul20: 173; RV32I: # %bb.0: 174; RV32I-NEXT: li a2, 20 175; RV32I-NEXT: mul a0, a0, a2 176; RV32I-NEXT: add a0, a0, a1 177; RV32I-NEXT: ret 178; 179; RV32XTHEADBA-LABEL: addmul20: 180; RV32XTHEADBA: # %bb.0: 181; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 2 182; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 2 183; RV32XTHEADBA-NEXT: ret 184 %c = mul i32 %a, 20 185 %d = add i32 %c, %b 186 ret i32 %d 187} 188 189define i32 @addmul24(i32 %a, i32 %b) { 190; RV32I-LABEL: addmul24: 191; RV32I: # %bb.0: 192; RV32I-NEXT: slli a2, a0, 3 193; RV32I-NEXT: slli a0, a0, 5 194; RV32I-NEXT: sub a0, a0, a2 195; RV32I-NEXT: add a0, a0, a1 196; RV32I-NEXT: ret 197; 198; RV32XTHEADBA-LABEL: addmul24: 199; RV32XTHEADBA: # %bb.0: 200; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 1 201; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 3 202; RV32XTHEADBA-NEXT: ret 203 %c = mul i32 %a, 24 204 %d = add i32 %c, %b 205 ret i32 %d 206} 207 208define i32 @addmul36(i32 %a, i32 %b) { 209; RV32I-LABEL: addmul36: 210; RV32I: # %bb.0: 211; RV32I-NEXT: li a2, 36 212; RV32I-NEXT: mul a0, a0, a2 213; RV32I-NEXT: add a0, a0, a1 214; RV32I-NEXT: ret 215; 216; RV32XTHEADBA-LABEL: addmul36: 217; RV32XTHEADBA: # %bb.0: 218; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 3 219; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 2 220; RV32XTHEADBA-NEXT: ret 221 %c = mul i32 %a, 36 222 %d = add i32 %c, %b 223 ret i32 %d 224} 225 226define i32 @addmul40(i32 %a, i32 %b) { 227; RV32I-LABEL: addmul40: 228; RV32I: # %bb.0: 229; RV32I-NEXT: li a2, 40 230; RV32I-NEXT: mul a0, a0, a2 231; RV32I-NEXT: add a0, a0, a1 232; RV32I-NEXT: ret 233; 234; RV32XTHEADBA-LABEL: addmul40: 235; RV32XTHEADBA: # %bb.0: 236; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 2 237; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 3 238; RV32XTHEADBA-NEXT: ret 239 %c = mul i32 %a, 40 240 %d = add i32 %c, %b 241 ret i32 %d 242} 243 244define i32 @addmul72(i32 %a, i32 %b) { 245; RV32I-LABEL: addmul72: 246; RV32I: # %bb.0: 247; RV32I-NEXT: li a2, 72 248; RV32I-NEXT: mul a0, a0, a2 249; RV32I-NEXT: add a0, a0, a1 250; RV32I-NEXT: ret 251; 252; RV32XTHEADBA-LABEL: addmul72: 253; RV32XTHEADBA: # %bb.0: 254; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 3 255; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 3 256; RV32XTHEADBA-NEXT: ret 257 %c = mul i32 %a, 72 258 %d = add i32 %c, %b 259 ret i32 %d 260} 261 262define i32 @mul96(i32 %a) { 263; RV32I-LABEL: mul96: 264; RV32I: # %bb.0: 265; RV32I-NEXT: slli a1, a0, 5 266; RV32I-NEXT: slli a0, a0, 7 267; RV32I-NEXT: sub a0, a0, a1 268; RV32I-NEXT: ret 269; 270; RV32XTHEADBA-LABEL: mul96: 271; RV32XTHEADBA: # %bb.0: 272; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 1 273; RV32XTHEADBA-NEXT: slli a0, a0, 5 274; RV32XTHEADBA-NEXT: ret 275 %c = mul i32 %a, 96 276 ret i32 %c 277} 278 279define i32 @mul160(i32 %a) { 280; RV32I-LABEL: mul160: 281; RV32I: # %bb.0: 282; RV32I-NEXT: li a1, 160 283; RV32I-NEXT: mul a0, a0, a1 284; RV32I-NEXT: ret 285; 286; RV32XTHEADBA-LABEL: mul160: 287; RV32XTHEADBA: # %bb.0: 288; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 2 289; RV32XTHEADBA-NEXT: slli a0, a0, 5 290; RV32XTHEADBA-NEXT: ret 291 %c = mul i32 %a, 160 292 ret i32 %c 293} 294 295define i32 @mul200(i32 %a) { 296; RV32I-LABEL: mul200: 297; RV32I: # %bb.0: 298; RV32I-NEXT: li a1, 200 299; RV32I-NEXT: mul a0, a0, a1 300; RV32I-NEXT: ret 301; 302; RV32XTHEADBA-LABEL: mul200: 303; RV32XTHEADBA: # %bb.0: 304; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 2 305; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 2 306; RV32XTHEADBA-NEXT: slli a0, a0, 3 307; RV32XTHEADBA-NEXT: ret 308 %c = mul i32 %a, 200 309 ret i32 %c 310} 311 312define i32 @mul288(i32 %a) { 313; RV32I-LABEL: mul288: 314; RV32I: # %bb.0: 315; RV32I-NEXT: li a1, 288 316; RV32I-NEXT: mul a0, a0, a1 317; RV32I-NEXT: ret 318; 319; RV32XTHEADBA-LABEL: mul288: 320; RV32XTHEADBA: # %bb.0: 321; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 3 322; RV32XTHEADBA-NEXT: slli a0, a0, 5 323; RV32XTHEADBA-NEXT: ret 324 %c = mul i32 %a, 288 325 ret i32 %c 326} 327 328define i32 @mul258(i32 %a) { 329; RV32I-LABEL: mul258: 330; RV32I: # %bb.0: 331; RV32I-NEXT: li a1, 258 332; RV32I-NEXT: mul a0, a0, a1 333; RV32I-NEXT: ret 334; 335; RV32XTHEADBA-LABEL: mul258: 336; RV32XTHEADBA: # %bb.0: 337; RV32XTHEADBA-NEXT: slli a1, a0, 8 338; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 1 339; RV32XTHEADBA-NEXT: ret 340 %c = mul i32 %a, 258 341 ret i32 %c 342} 343 344define i32 @mul260(i32 %a) { 345; RV32I-LABEL: mul260: 346; RV32I: # %bb.0: 347; RV32I-NEXT: li a1, 260 348; RV32I-NEXT: mul a0, a0, a1 349; RV32I-NEXT: ret 350; 351; RV32XTHEADBA-LABEL: mul260: 352; RV32XTHEADBA: # %bb.0: 353; RV32XTHEADBA-NEXT: slli a1, a0, 8 354; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 2 355; RV32XTHEADBA-NEXT: ret 356 %c = mul i32 %a, 260 357 ret i32 %c 358} 359 360define i32 @mul264(i32 %a) { 361; RV32I-LABEL: mul264: 362; RV32I: # %bb.0: 363; RV32I-NEXT: li a1, 264 364; RV32I-NEXT: mul a0, a0, a1 365; RV32I-NEXT: ret 366; 367; RV32XTHEADBA-LABEL: mul264: 368; RV32XTHEADBA: # %bb.0: 369; RV32XTHEADBA-NEXT: slli a1, a0, 8 370; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 3 371; RV32XTHEADBA-NEXT: ret 372 %c = mul i32 %a, 264 373 ret i32 %c 374} 375 376define i32 @mul11(i32 %a) { 377; RV32I-LABEL: mul11: 378; RV32I: # %bb.0: 379; RV32I-NEXT: li a1, 11 380; RV32I-NEXT: mul a0, a0, a1 381; RV32I-NEXT: ret 382; 383; RV32XTHEADBA-LABEL: mul11: 384; RV32XTHEADBA: # %bb.0: 385; RV32XTHEADBA-NEXT: th.addsl a1, a0, a0, 2 386; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 1 387; RV32XTHEADBA-NEXT: ret 388 %c = mul i32 %a, 11 389 ret i32 %c 390} 391 392define i32 @mul19(i32 %a) { 393; RV32I-LABEL: mul19: 394; RV32I: # %bb.0: 395; RV32I-NEXT: li a1, 19 396; RV32I-NEXT: mul a0, a0, a1 397; RV32I-NEXT: ret 398; 399; RV32XTHEADBA-LABEL: mul19: 400; RV32XTHEADBA: # %bb.0: 401; RV32XTHEADBA-NEXT: th.addsl a1, a0, a0, 3 402; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 1 403; RV32XTHEADBA-NEXT: ret 404 %c = mul i32 %a, 19 405 ret i32 %c 406} 407 408define i32 @mul13(i32 %a) { 409; RV32I-LABEL: mul13: 410; RV32I: # %bb.0: 411; RV32I-NEXT: li a1, 13 412; RV32I-NEXT: mul a0, a0, a1 413; RV32I-NEXT: ret 414; 415; RV32XTHEADBA-LABEL: mul13: 416; RV32XTHEADBA: # %bb.0: 417; RV32XTHEADBA-NEXT: th.addsl a1, a0, a0, 1 418; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 2 419; RV32XTHEADBA-NEXT: ret 420 %c = mul i32 %a, 13 421 ret i32 %c 422} 423 424define i32 @mul21(i32 %a) { 425; RV32I-LABEL: mul21: 426; RV32I: # %bb.0: 427; RV32I-NEXT: li a1, 21 428; RV32I-NEXT: mul a0, a0, a1 429; RV32I-NEXT: ret 430; 431; RV32XTHEADBA-LABEL: mul21: 432; RV32XTHEADBA: # %bb.0: 433; RV32XTHEADBA-NEXT: th.addsl a1, a0, a0, 2 434; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 2 435; RV32XTHEADBA-NEXT: ret 436 %c = mul i32 %a, 21 437 ret i32 %c 438} 439 440define i32 @mul37(i32 %a) { 441; RV32I-LABEL: mul37: 442; RV32I: # %bb.0: 443; RV32I-NEXT: li a1, 37 444; RV32I-NEXT: mul a0, a0, a1 445; RV32I-NEXT: ret 446; 447; RV32XTHEADBA-LABEL: mul37: 448; RV32XTHEADBA: # %bb.0: 449; RV32XTHEADBA-NEXT: th.addsl a1, a0, a0, 3 450; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 2 451; RV32XTHEADBA-NEXT: ret 452 %c = mul i32 %a, 37 453 ret i32 %c 454} 455 456define i32 @mul25(i32 %a) { 457; RV32I-LABEL: mul25: 458; RV32I: # %bb.0: 459; RV32I-NEXT: li a1, 25 460; RV32I-NEXT: mul a0, a0, a1 461; RV32I-NEXT: ret 462; 463; RV32XTHEADBA-LABEL: mul25: 464; RV32XTHEADBA: # %bb.0: 465; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 2 466; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 2 467; RV32XTHEADBA-NEXT: ret 468 %c = mul i32 %a, 25 469 ret i32 %c 470} 471 472define i32 @mul41(i32 %a) { 473; RV32I-LABEL: mul41: 474; RV32I: # %bb.0: 475; RV32I-NEXT: li a1, 41 476; RV32I-NEXT: mul a0, a0, a1 477; RV32I-NEXT: ret 478; 479; RV32XTHEADBA-LABEL: mul41: 480; RV32XTHEADBA: # %bb.0: 481; RV32XTHEADBA-NEXT: th.addsl a1, a0, a0, 2 482; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 3 483; RV32XTHEADBA-NEXT: ret 484 %c = mul i32 %a, 41 485 ret i32 %c 486} 487 488define i32 @mul73(i32 %a) { 489; RV32I-LABEL: mul73: 490; RV32I: # %bb.0: 491; RV32I-NEXT: li a1, 73 492; RV32I-NEXT: mul a0, a0, a1 493; RV32I-NEXT: ret 494; 495; RV32XTHEADBA-LABEL: mul73: 496; RV32XTHEADBA: # %bb.0: 497; RV32XTHEADBA-NEXT: th.addsl a1, a0, a0, 3 498; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 3 499; RV32XTHEADBA-NEXT: ret 500 %c = mul i32 %a, 73 501 ret i32 %c 502} 503 504define i32 @mul27(i32 %a) { 505; RV32I-LABEL: mul27: 506; RV32I: # %bb.0: 507; RV32I-NEXT: li a1, 27 508; RV32I-NEXT: mul a0, a0, a1 509; RV32I-NEXT: ret 510; 511; RV32XTHEADBA-LABEL: mul27: 512; RV32XTHEADBA: # %bb.0: 513; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 1 514; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 3 515; RV32XTHEADBA-NEXT: ret 516 %c = mul i32 %a, 27 517 ret i32 %c 518} 519 520define i32 @mul45(i32 %a) { 521; RV32I-LABEL: mul45: 522; RV32I: # %bb.0: 523; RV32I-NEXT: li a1, 45 524; RV32I-NEXT: mul a0, a0, a1 525; RV32I-NEXT: ret 526; 527; RV32XTHEADBA-LABEL: mul45: 528; RV32XTHEADBA: # %bb.0: 529; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 2 530; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 3 531; RV32XTHEADBA-NEXT: ret 532 %c = mul i32 %a, 45 533 ret i32 %c 534} 535 536define i32 @mul81(i32 %a) { 537; RV32I-LABEL: mul81: 538; RV32I: # %bb.0: 539; RV32I-NEXT: li a1, 81 540; RV32I-NEXT: mul a0, a0, a1 541; RV32I-NEXT: ret 542; 543; RV32XTHEADBA-LABEL: mul81: 544; RV32XTHEADBA: # %bb.0: 545; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 3 546; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 3 547; RV32XTHEADBA-NEXT: ret 548 %c = mul i32 %a, 81 549 ret i32 %c 550} 551 552define i32 @mul4098(i32 %a) { 553; RV32I-LABEL: mul4098: 554; RV32I: # %bb.0: 555; RV32I-NEXT: slli a1, a0, 1 556; RV32I-NEXT: slli a0, a0, 12 557; RV32I-NEXT: add a0, a0, a1 558; RV32I-NEXT: ret 559; 560; RV32XTHEADBA-LABEL: mul4098: 561; RV32XTHEADBA: # %bb.0: 562; RV32XTHEADBA-NEXT: slli a1, a0, 12 563; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 1 564; RV32XTHEADBA-NEXT: ret 565 %c = mul i32 %a, 4098 566 ret i32 %c 567} 568 569define i32 @mul4100(i32 %a) { 570; RV32I-LABEL: mul4100: 571; RV32I: # %bb.0: 572; RV32I-NEXT: slli a1, a0, 2 573; RV32I-NEXT: slli a0, a0, 12 574; RV32I-NEXT: add a0, a0, a1 575; RV32I-NEXT: ret 576; 577; RV32XTHEADBA-LABEL: mul4100: 578; RV32XTHEADBA: # %bb.0: 579; RV32XTHEADBA-NEXT: slli a1, a0, 12 580; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 2 581; RV32XTHEADBA-NEXT: ret 582 %c = mul i32 %a, 4100 583 ret i32 %c 584} 585 586define i32 @mul4104(i32 %a) { 587; RV32I-LABEL: mul4104: 588; RV32I: # %bb.0: 589; RV32I-NEXT: slli a1, a0, 3 590; RV32I-NEXT: slli a0, a0, 12 591; RV32I-NEXT: add a0, a0, a1 592; RV32I-NEXT: ret 593; 594; RV32XTHEADBA-LABEL: mul4104: 595; RV32XTHEADBA: # %bb.0: 596; RV32XTHEADBA-NEXT: slli a1, a0, 12 597; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 3 598; RV32XTHEADBA-NEXT: ret 599 %c = mul i32 %a, 4104 600 ret i32 %c 601} 602 603define i32 @add4104(i32 %a) { 604; RV32I-LABEL: add4104: 605; RV32I: # %bb.0: 606; RV32I-NEXT: lui a1, 1 607; RV32I-NEXT: addi a1, a1, 8 608; RV32I-NEXT: add a0, a0, a1 609; RV32I-NEXT: ret 610; 611; RV32XTHEADBA-LABEL: add4104: 612; RV32XTHEADBA: # %bb.0: 613; RV32XTHEADBA-NEXT: li a1, 1026 614; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 2 615; RV32XTHEADBA-NEXT: ret 616 %c = add i32 %a, 4104 617 ret i32 %c 618} 619 620define i32 @add8208(i32 %a) { 621; RV32I-LABEL: add8208: 622; RV32I: # %bb.0: 623; RV32I-NEXT: lui a1, 2 624; RV32I-NEXT: addi a1, a1, 16 625; RV32I-NEXT: add a0, a0, a1 626; RV32I-NEXT: ret 627; 628; RV32XTHEADBA-LABEL: add8208: 629; RV32XTHEADBA: # %bb.0: 630; RV32XTHEADBA-NEXT: li a1, 1026 631; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 3 632; RV32XTHEADBA-NEXT: ret 633 %c = add i32 %a, 8208 634 ret i32 %c 635} 636 637define i32 @add8192(i32 %a) { 638; CHECK-LABEL: add8192: 639; CHECK: # %bb.0: 640; CHECK-NEXT: lui a1, 2 641; CHECK-NEXT: add a0, a0, a1 642; CHECK-NEXT: ret 643 %c = add i32 %a, 8192 644 ret i32 %c 645} 646 647define i32 @addshl_5_6(i32 %a, i32 %b) { 648; CHECK-LABEL: addshl_5_6: 649; CHECK: # %bb.0: 650; CHECK-NEXT: slli a0, a0, 5 651; CHECK-NEXT: slli a1, a1, 6 652; CHECK-NEXT: add a0, a0, a1 653; CHECK-NEXT: ret 654 %c = shl i32 %a, 5 655 %d = shl i32 %b, 6 656 %e = add i32 %c, %d 657 ret i32 %e 658} 659 660define i32 @addshl_5_7(i32 %a, i32 %b) { 661; CHECK-LABEL: addshl_5_7: 662; CHECK: # %bb.0: 663; CHECK-NEXT: slli a0, a0, 5 664; CHECK-NEXT: slli a1, a1, 7 665; CHECK-NEXT: add a0, a0, a1 666; CHECK-NEXT: ret 667 %c = shl i32 %a, 5 668 %d = shl i32 %b, 7 669 %e = add i32 %c, %d 670 ret i32 %e 671} 672 673define i32 @addshl_5_8(i32 %a, i32 %b) { 674; CHECK-LABEL: addshl_5_8: 675; CHECK: # %bb.0: 676; CHECK-NEXT: slli a0, a0, 5 677; CHECK-NEXT: slli a1, a1, 8 678; CHECK-NEXT: add a0, a0, a1 679; CHECK-NEXT: ret 680 %c = shl i32 %a, 5 681 %d = shl i32 %b, 8 682 %e = add i32 %c, %d 683 ret i32 %e 684} 685 686define i32 @srli_1_sh2add(ptr %0, i32 %1) { 687; RV32I-LABEL: srli_1_sh2add: 688; RV32I: # %bb.0: 689; RV32I-NEXT: slli a1, a1, 1 690; RV32I-NEXT: andi a1, a1, -4 691; RV32I-NEXT: add a0, a0, a1 692; RV32I-NEXT: lw a0, 0(a0) 693; RV32I-NEXT: ret 694; 695; RV32XTHEADBA-LABEL: srli_1_sh2add: 696; RV32XTHEADBA: # %bb.0: 697; RV32XTHEADBA-NEXT: srli a1, a1, 1 698; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 2 699; RV32XTHEADBA-NEXT: lw a0, 0(a0) 700; RV32XTHEADBA-NEXT: ret 701 %3 = lshr i32 %1, 1 702 %4 = getelementptr inbounds i32, ptr %0, i32 %3 703 %5 = load i32, ptr %4, align 4 704 ret i32 %5 705} 706 707define i64 @srli_2_sh3add(ptr %0, i32 %1) { 708; RV32I-LABEL: srli_2_sh3add: 709; RV32I: # %bb.0: 710; RV32I-NEXT: slli a1, a1, 1 711; RV32I-NEXT: andi a1, a1, -8 712; RV32I-NEXT: add a1, a0, a1 713; RV32I-NEXT: lw a0, 0(a1) 714; RV32I-NEXT: lw a1, 4(a1) 715; RV32I-NEXT: ret 716; 717; RV32XTHEADBA-LABEL: srli_2_sh3add: 718; RV32XTHEADBA: # %bb.0: 719; RV32XTHEADBA-NEXT: srli a1, a1, 2 720; RV32XTHEADBA-NEXT: th.addsl a1, a0, a1, 3 721; RV32XTHEADBA-NEXT: lw a0, 0(a1) 722; RV32XTHEADBA-NEXT: lw a1, 4(a1) 723; RV32XTHEADBA-NEXT: ret 724 %3 = lshr i32 %1, 2 725 %4 = getelementptr inbounds i64, ptr %0, i32 %3 726 %5 = load i64, ptr %4, align 8 727 ret i64 %5 728} 729 730define signext i16 @srli_2_sh1add(ptr %0, i32 %1) { 731; RV32I-LABEL: srli_2_sh1add: 732; RV32I: # %bb.0: 733; RV32I-NEXT: srli a1, a1, 1 734; RV32I-NEXT: andi a1, a1, -2 735; RV32I-NEXT: add a0, a0, a1 736; RV32I-NEXT: lh a0, 0(a0) 737; RV32I-NEXT: ret 738; 739; RV32XTHEADBA-LABEL: srli_2_sh1add: 740; RV32XTHEADBA: # %bb.0: 741; RV32XTHEADBA-NEXT: srli a1, a1, 2 742; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 1 743; RV32XTHEADBA-NEXT: lh a0, 0(a0) 744; RV32XTHEADBA-NEXT: ret 745 %3 = lshr i32 %1, 2 746 %4 = getelementptr inbounds i16, ptr %0, i32 %3 747 %5 = load i16, ptr %4, align 2 748 ret i16 %5 749} 750 751define i32 @srli_3_sh2add(ptr %0, i32 %1) { 752; RV32I-LABEL: srli_3_sh2add: 753; RV32I: # %bb.0: 754; RV32I-NEXT: srli a1, a1, 1 755; RV32I-NEXT: andi a1, a1, -4 756; RV32I-NEXT: add a0, a0, a1 757; RV32I-NEXT: lw a0, 0(a0) 758; RV32I-NEXT: ret 759; 760; RV32XTHEADBA-LABEL: srli_3_sh2add: 761; RV32XTHEADBA: # %bb.0: 762; RV32XTHEADBA-NEXT: srli a1, a1, 3 763; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 2 764; RV32XTHEADBA-NEXT: lw a0, 0(a0) 765; RV32XTHEADBA-NEXT: ret 766 %3 = lshr i32 %1, 3 767 %4 = getelementptr inbounds i32, ptr %0, i32 %3 768 %5 = load i32, ptr %4, align 4 769 ret i32 %5 770} 771 772define i64 @srli_4_sh3add(ptr %0, i32 %1) { 773; RV32I-LABEL: srli_4_sh3add: 774; RV32I: # %bb.0: 775; RV32I-NEXT: srli a1, a1, 1 776; RV32I-NEXT: andi a1, a1, -8 777; RV32I-NEXT: add a1, a0, a1 778; RV32I-NEXT: lw a0, 0(a1) 779; RV32I-NEXT: lw a1, 4(a1) 780; RV32I-NEXT: ret 781; 782; RV32XTHEADBA-LABEL: srli_4_sh3add: 783; RV32XTHEADBA: # %bb.0: 784; RV32XTHEADBA-NEXT: srli a1, a1, 4 785; RV32XTHEADBA-NEXT: th.addsl a1, a0, a1, 3 786; RV32XTHEADBA-NEXT: lw a0, 0(a1) 787; RV32XTHEADBA-NEXT: lw a1, 4(a1) 788; RV32XTHEADBA-NEXT: ret 789 %3 = lshr i32 %1, 4 790 %4 = getelementptr inbounds i64, ptr %0, i32 %3 791 %5 = load i64, ptr %4, align 8 792 ret i64 %5 793} 794 795define i32 @mul_neg1(i32 %a) { 796; CHECK-LABEL: mul_neg1: 797; CHECK: # %bb.0: 798; CHECK-NEXT: neg a0, a0 799; CHECK-NEXT: ret 800 %c = mul i32 %a, -1 801 ret i32 %c 802} 803 804define i32 @mul_neg2(i32 %a) { 805; CHECK-LABEL: mul_neg2: 806; CHECK: # %bb.0: 807; CHECK-NEXT: slli a0, a0, 1 808; CHECK-NEXT: neg a0, a0 809; CHECK-NEXT: ret 810 %c = mul i32 %a, -2 811 ret i32 %c 812} 813 814define i32 @mul_neg3(i32 %a) { 815; RV32I-LABEL: mul_neg3: 816; RV32I: # %bb.0: 817; RV32I-NEXT: slli a1, a0, 1 818; RV32I-NEXT: neg a0, a0 819; RV32I-NEXT: sub a0, a0, a1 820; RV32I-NEXT: ret 821; 822; RV32XTHEADBA-LABEL: mul_neg3: 823; RV32XTHEADBA: # %bb.0: 824; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 1 825; RV32XTHEADBA-NEXT: neg a0, a0 826; RV32XTHEADBA-NEXT: ret 827 %c = mul i32 %a, -3 828 ret i32 %c 829} 830 831define i32 @mul_neg4(i32 %a) { 832; CHECK-LABEL: mul_neg4: 833; CHECK: # %bb.0: 834; CHECK-NEXT: slli a0, a0, 2 835; CHECK-NEXT: neg a0, a0 836; CHECK-NEXT: ret 837 %c = mul i32 %a, -4 838 ret i32 %c 839} 840 841define i32 @mul_neg5(i32 %a) { 842; RV32I-LABEL: mul_neg5: 843; RV32I: # %bb.0: 844; RV32I-NEXT: slli a1, a0, 2 845; RV32I-NEXT: neg a0, a0 846; RV32I-NEXT: sub a0, a0, a1 847; RV32I-NEXT: ret 848; 849; RV32XTHEADBA-LABEL: mul_neg5: 850; RV32XTHEADBA: # %bb.0: 851; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 2 852; RV32XTHEADBA-NEXT: neg a0, a0 853; RV32XTHEADBA-NEXT: ret 854 %c = mul i32 %a, -5 855 ret i32 %c 856} 857 858define i32 @mul_neg6(i32 %a) { 859; CHECK-LABEL: mul_neg6: 860; CHECK: # %bb.0: 861; CHECK-NEXT: li a1, -6 862; CHECK-NEXT: mul a0, a0, a1 863; CHECK-NEXT: ret 864 %c = mul i32 %a, -6 865 ret i32 %c 866} 867 868define i32 @mul_neg7(i32 %a) { 869; CHECK-LABEL: mul_neg7: 870; CHECK: # %bb.0: 871; CHECK-NEXT: slli a1, a0, 3 872; CHECK-NEXT: sub a0, a0, a1 873; CHECK-NEXT: ret 874 %c = mul i32 %a, -7 875 ret i32 %c 876} 877 878define i32 @mul_neg8(i32 %a) { 879; CHECK-LABEL: mul_neg8: 880; CHECK: # %bb.0: 881; CHECK-NEXT: slli a0, a0, 3 882; CHECK-NEXT: neg a0, a0 883; CHECK-NEXT: ret 884 %c = mul i32 %a, -8 885 ret i32 %c 886} 887