105041b78SPiyou Chen; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -verify-machineinstrs < %s | FileCheck %s 205041b78SPiyou Chen 305041b78SPiyou Chen; CHECK: .option push 405041b78SPiyou Chen; CHECK-NEXT: .option arch, +v, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b 505041b78SPiyou Chendefine void @test1() "target-features"="+a,+d,+f,+m,+c,+v,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" { 605041b78SPiyou Chen; CHECK-LABEL: test1 705041b78SPiyou Chen; CHECK: .option pop 805041b78SPiyou Chenentry: 905041b78SPiyou Chen ret void 1005041b78SPiyou Chen} 1105041b78SPiyou Chen 1205041b78SPiyou Chen; CHECK: .option push 138901eb28SJianjian GUAN; CHECK-NEXT: .option arch, +zihintntl 148901eb28SJianjian GUANdefine void @test2() "target-features"="+a,+d,+f,+m,+zihintntl,+zifencei" { 1505041b78SPiyou Chen; CHECK-LABEL: test2 1605041b78SPiyou Chen; CHECK: .option pop 1705041b78SPiyou Chenentry: 1805041b78SPiyou Chen ret void 1905041b78SPiyou Chen} 2005041b78SPiyou Chen 2105041b78SPiyou Chen; CHECK: .option push 2205041b78SPiyou Chen; CHECK-NEXT: .option arch, -a, -d, -f, -m 2305041b78SPiyou Chendefine void @test3() "target-features"="-a,-d,-f,-m" { 2405041b78SPiyou Chen; CHECK-LABEL: test3 2505041b78SPiyou Chen; CHECK: .option pop 2605041b78SPiyou Chenentry: 2705041b78SPiyou Chen ret void 2805041b78SPiyou Chen} 2905041b78SPiyou Chen 3005041b78SPiyou Chen; CHECK-NOT: .option push 3105041b78SPiyou Chendefine void @test4() { 3205041b78SPiyou Chen; CHECK-LABEL: test4 3305041b78SPiyou Chen; CHECK-NOT: .option pop 3405041b78SPiyou Chenentry: 3505041b78SPiyou Chen ret void 3605041b78SPiyou Chen} 37d861b318SPiyou Chen 38b83a1ed5SPiyou Chen; CHECK-NOT: .option push 39*9067070dSCraig Topperdefine void @test5() "target-features"="+unaligned-scalar-mem" { 40d861b318SPiyou Chen; CHECK-LABEL: test5 41b83a1ed5SPiyou Chen; CHECK-NOT: .option pop 42d861b318SPiyou Chenentry: 43d861b318SPiyou Chen ret void 44d861b318SPiyou Chen} 45