1; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -verify-machineinstrs < %s | FileCheck %s 2 3; CHECK: .option push 4; CHECK-NEXT: .option arch, +v, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b 5define void @test1() "target-features"="+a,+d,+f,+m,+c,+v,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" { 6; CHECK-LABEL: test1 7; CHECK: .option pop 8entry: 9 ret void 10} 11 12; CHECK: .option push 13; CHECK-NEXT: .option arch, +zihintntl 14define void @test2() "target-features"="+a,+d,+f,+m,+zihintntl,+zifencei" { 15; CHECK-LABEL: test2 16; CHECK: .option pop 17entry: 18 ret void 19} 20 21; CHECK: .option push 22; CHECK-NEXT: .option arch, -a, -d, -f, -m 23define void @test3() "target-features"="-a,-d,-f,-m" { 24; CHECK-LABEL: test3 25; CHECK: .option pop 26entry: 27 ret void 28} 29 30; CHECK-NOT: .option push 31define void @test4() { 32; CHECK-LABEL: test4 33; CHECK-NOT: .option pop 34entry: 35 ret void 36} 37 38; CHECK-NOT: .option push 39define void @test5() "target-features"="+unaligned-scalar-mem" { 40; CHECK-LABEL: test5 41; CHECK-NOT: .option pop 42entry: 43 ret void 44} 45