1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \ 3; RUN: | FileCheck -check-prefix=RV64I %s 4 5@PL_reg_match_utf8 = external global i8, align 1 6 7declare signext i32 @test1(i8 signext) 8 9declare signext i32 @test2(i8 signext) 10 11declare signext i32 @test3(i8 signext) 12 13define signext i32 @test() nounwind { 14; RV64I-LABEL: test: 15; RV64I: # %bb.0: 16; RV64I-NEXT: addi sp, sp, -16 17; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 18; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill 19; RV64I-NEXT: lui a0, %hi(PL_reg_match_utf8) 20; RV64I-NEXT: lb s0, %lo(PL_reg_match_utf8)(a0) 21; RV64I-NEXT: beqz s0, .LBB0_2 22; RV64I-NEXT: # %bb.1: 23; RV64I-NEXT: mv a0, s0 24; RV64I-NEXT: call test1 25; RV64I-NEXT: mv a0, s0 26; RV64I-NEXT: call test2 27; RV64I-NEXT: mv a0, s0 28; RV64I-NEXT: call test3 29; RV64I-NEXT: j .LBB0_3 30; RV64I-NEXT: .LBB0_2: 31; RV64I-NEXT: li a0, 0 32; RV64I-NEXT: call test2 33; RV64I-NEXT: .LBB0_3: 34; RV64I-NEXT: li a0, 0 35; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 36; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload 37; RV64I-NEXT: addi sp, sp, 16 38; RV64I-NEXT: ret 39 %1 = load i8, ptr @PL_reg_match_utf8, align 1 40 %2 = icmp eq i8 %1, 0 41 br i1 %2, label %7, label %3 42 433: 44 %4 = tail call signext i32 @test1(i8 signext %1) 45 %5 = tail call signext i32 @test2(i8 signext %1) 46 %6 = tail call signext i32 @test3(i8 signext %1) 47 br label %9 48 497: 50 %8 = tail call signext i32 @test2(i8 signext 0) 51 br label %9 52 539: 54 ret i32 0 55} 56 57 58define signext i32 @test_loop() nounwind { 59; RV64I-LABEL: test_loop: 60; RV64I: # %bb.0: 61; RV64I-NEXT: addi sp, sp, -32 62; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill 63; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill 64; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill 65; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill 66; RV64I-NEXT: li s1, -16 67; RV64I-NEXT: lui s2, %hi(PL_reg_match_utf8) 68; RV64I-NEXT: j .LBB1_2 69; RV64I-NEXT: .LBB1_1: # in Loop: Header=BB1_2 Depth=1 70; RV64I-NEXT: mv a0, s0 71; RV64I-NEXT: call test2 72; RV64I-NEXT: addiw s1, s1, 1 73; RV64I-NEXT: beqz s1, .LBB1_4 74; RV64I-NEXT: .LBB1_2: # =>This Inner Loop Header: Depth=1 75; RV64I-NEXT: lb s0, %lo(PL_reg_match_utf8)(s2) 76; RV64I-NEXT: beqz s0, .LBB1_1 77; RV64I-NEXT: # %bb.3: # in Loop: Header=BB1_2 Depth=1 78; RV64I-NEXT: mv a0, s0 79; RV64I-NEXT: call test1 80; RV64I-NEXT: mv a0, s0 81; RV64I-NEXT: call test2 82; RV64I-NEXT: mv a0, s0 83; RV64I-NEXT: call test3 84; RV64I-NEXT: addiw s1, s1, 1 85; RV64I-NEXT: bnez s1, .LBB1_2 86; RV64I-NEXT: .LBB1_4: 87; RV64I-NEXT: li a0, 0 88; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload 89; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload 90; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload 91; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload 92; RV64I-NEXT: addi sp, sp, 32 93; RV64I-NEXT: ret 94 br label %1 95 961: 97 %2 = phi i32 [ 16, %0 ], [ %12, %11 ] 98 %3 = load i8, ptr @PL_reg_match_utf8, align 1 99 %4 = icmp eq i8 %3, 0 100 br i1 %4, label %9, label %5 101 1025: 103 %6 = tail call signext i32 @test1(i8 signext %3) 104 %7 = tail call signext i32 @test2(i8 signext %3) 105 %8 = tail call signext i32 @test3(i8 signext %3) 106 br label %11 107 1089: 109 %10 = tail call signext i32 @test2(i8 signext %3) 110 br label %11 111 11211: 113 %12 = add nsw i32 %2, -1 114 %13 = icmp eq i32 %12, 0 115 br i1 %13, label %14, label %1 116 11714: 118 ret i32 0 119} 120