xref: /llvm-project/llvm/test/CodeGen/RISCV/pr96366.ll (revision d5c9ffd545ebf171346ac69b15fafeee469f0b3c)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
3
4declare void @use(i32)
5
6define i32 @f(i32 %x) nounwind {
7; CHECK-LABEL: f:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    addi sp, sp, -16
10; CHECK-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
11; CHECK-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
12; CHECK-NEXT:    mv s0, a0
13; CHECK-NEXT:    negw a0, a0
14; CHECK-NEXT:    call use
15; CHECK-NEXT:    li a0, 4
16; CHECK-NEXT:    subw a0, a0, s0
17; CHECK-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
18; CHECK-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
19; CHECK-NEXT:    addi sp, sp, 16
20; CHECK-NEXT:    ret
21  %sub1 = sub nuw i32 0, %x
22  call void @use(i32 %sub1)
23  %sub2 = sub i32 1, %x
24  %sub3 = sub i32 3, %x
25  %mul = mul i32 %x, 1
26  %add1 = add i32 %sub2, %mul
27  %add2 = add i32 %add1, %sub3
28  ret i32 %add2
29}
30