1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck -check-prefix=RV32I %s 3; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck -check-prefix=RV64I %s 4 5; regression due to creation of temporary i32 avgfloors node 6define signext i64 @PR95284(i32 signext %0) { 7; RV32I-LABEL: PR95284: 8; RV32I: # %bb.0: # %entry 9; RV32I-NEXT: addi a1, a0, -1 10; RV32I-NEXT: seqz a0, a0 11; RV32I-NEXT: slli a2, a0, 31 12; RV32I-NEXT: srli a1, a1, 1 13; RV32I-NEXT: or a1, a1, a2 14; RV32I-NEXT: addi a1, a1, 1 15; RV32I-NEXT: seqz a2, a1 16; RV32I-NEXT: sub a2, a2, a0 17; RV32I-NEXT: andi a0, a1, -2 18; RV32I-NEXT: slli a1, a2, 1 19; RV32I-NEXT: srli a1, a1, 1 20; RV32I-NEXT: ret 21; 22; RV64I-LABEL: PR95284: 23; RV64I: # %bb.0: # %entry 24; RV64I-NEXT: addi a0, a0, -1 25; RV64I-NEXT: srli a0, a0, 1 26; RV64I-NEXT: addi a0, a0, 1 27; RV64I-NEXT: andi a0, a0, -2 28; RV64I-NEXT: ret 29entry: 30 %1 = zext nneg i32 %0 to i64 31 %2 = add nsw i64 %1, -1 32 %3 = lshr i64 %2, 1 33 %4 = add nuw nsw i64 %3, 1 34 %5 = and i64 %4, 9223372036854775806 35 ret i64 %5 36} 37