1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck -check-prefix=RV32I %s 3; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck -check-prefix=RV64I %s 4 5define i32 @PR95271(ptr %p) { 6; RV32I-LABEL: PR95271: 7; RV32I: # %bb.0: 8; RV32I-NEXT: lw a0, 0(a0) 9; RV32I-NEXT: lui a1, 349525 10; RV32I-NEXT: addi a1, a1, 1365 11; RV32I-NEXT: addi a0, a0, 1 12; RV32I-NEXT: srli a2, a0, 1 13; RV32I-NEXT: and a1, a2, a1 14; RV32I-NEXT: lui a2, 209715 15; RV32I-NEXT: addi a2, a2, 819 16; RV32I-NEXT: sub a0, a0, a1 17; RV32I-NEXT: and a1, a0, a2 18; RV32I-NEXT: srli a0, a0, 2 19; RV32I-NEXT: and a0, a0, a2 20; RV32I-NEXT: lui a2, 61681 21; RV32I-NEXT: add a0, a1, a0 22; RV32I-NEXT: srli a1, a0, 4 23; RV32I-NEXT: add a0, a0, a1 24; RV32I-NEXT: addi a1, a2, -241 25; RV32I-NEXT: and a0, a0, a1 26; RV32I-NEXT: slli a1, a0, 8 27; RV32I-NEXT: add a0, a0, a1 28; RV32I-NEXT: slli a1, a0, 16 29; RV32I-NEXT: add a0, a0, a1 30; RV32I-NEXT: srli a0, a0, 24 31; RV32I-NEXT: ret 32; 33; RV64I-LABEL: PR95271: 34; RV64I: # %bb.0: 35; RV64I-NEXT: lw a0, 0(a0) 36; RV64I-NEXT: lui a1, 349525 37; RV64I-NEXT: addiw a1, a1, 1365 38; RV64I-NEXT: addi a2, a0, 1 39; RV64I-NEXT: srli a2, a2, 1 40; RV64I-NEXT: and a1, a2, a1 41; RV64I-NEXT: lui a2, 209715 42; RV64I-NEXT: addiw a2, a2, 819 43; RV64I-NEXT: addiw a0, a0, 1 44; RV64I-NEXT: sub a0, a0, a1 45; RV64I-NEXT: and a1, a0, a2 46; RV64I-NEXT: srli a0, a0, 2 47; RV64I-NEXT: and a0, a0, a2 48; RV64I-NEXT: lui a2, 61681 49; RV64I-NEXT: add a0, a1, a0 50; RV64I-NEXT: srli a1, a0, 4 51; RV64I-NEXT: add a0, a0, a1 52; RV64I-NEXT: addi a1, a2, -241 53; RV64I-NEXT: and a0, a0, a1 54; RV64I-NEXT: slli a1, a0, 8 55; RV64I-NEXT: add a0, a0, a1 56; RV64I-NEXT: slli a1, a0, 16 57; RV64I-NEXT: add a0, a0, a1 58; RV64I-NEXT: srliw a0, a0, 24 59; RV64I-NEXT: ret 60 %load = load i32, ptr %p, align 4 61 %inc = add i32 %load, 1 62 %pop = tail call i32 @llvm.ctpop.i32(i32 %inc) 63 ret i32 %pop 64} 65