1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=riscv32-- -mattr=+v | FileCheck -check-prefix=RV32I %s 3; RUN: llc < %s -mtriple=riscv64-- -mattr=+v | FileCheck -check-prefix=RV64I %s 4; RUN: llc < %s -mtriple=riscv32-- -mattr=+zve32x,+zvl128b | FileCheck -check-prefix=RV32I %s 5; RUN: llc < %s -mtriple=riscv64-- -mattr=+zve32x,+zvl128b | FileCheck -check-prefix=RV64I %s 6 7define <8 x i16> @PR94265(<8 x i32> %a0) #0 { 8; RV32I-LABEL: PR94265: 9; RV32I: # %bb.0: 10; RV32I-NEXT: vsetivli zero, 8, e32, m2, ta, ma 11; RV32I-NEXT: vsra.vi v10, v8, 31 12; RV32I-NEXT: vsrl.vi v10, v10, 26 13; RV32I-NEXT: vadd.vv v8, v8, v10 14; RV32I-NEXT: vsetvli zero, zero, e16, m1, ta, ma 15; RV32I-NEXT: vnsrl.wi v10, v8, 6 16; RV32I-NEXT: vsll.vi v8, v10, 10 17; RV32I-NEXT: ret 18; 19; RV64I-LABEL: PR94265: 20; RV64I: # %bb.0: 21; RV64I-NEXT: vsetivli zero, 8, e32, m2, ta, ma 22; RV64I-NEXT: vsra.vi v10, v8, 31 23; RV64I-NEXT: vsrl.vi v10, v10, 26 24; RV64I-NEXT: vadd.vv v8, v8, v10 25; RV64I-NEXT: vsetvli zero, zero, e16, m1, ta, ma 26; RV64I-NEXT: vnsrl.wi v10, v8, 6 27; RV64I-NEXT: vsll.vi v8, v10, 10 28; RV64I-NEXT: ret 29 %t1 = sdiv <8 x i32> %a0, <i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64> 30 %t2 = trunc <8 x i32> %t1 to <8 x i16> 31 %t3 = shl <8 x i16> %t2, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10> 32 ret <8 x i16> %t3 33} 34