xref: /llvm-project/llvm/test/CodeGen/RISCV/pr94145.ll (revision c9a86fa9a631eb77f229e457a323caec705600bf)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=riscv32-- | FileCheck %s
3; RUN: llc < %s -mtriple=riscv64-- | FileCheck %s
4
5define i32 @PR94145(i16 %a0) {
6; CHECK-LABEL: PR94145:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    andi a0, a0, 2
9; CHECK-NEXT:    seqz a0, a0
10; CHECK-NEXT:    li a1, 1
11; CHECK-NEXT:    sll a0, a1, a0
12; CHECK-NEXT:    ret
13  %lshr = lshr i16 %a0, 1
14  %and = and i16 %lshr, 1
15  %xor = xor i16 %and, 1
16  %shl = shl i16 1, %xor
17  %freeze = freeze i16 %shl
18  %zext = zext i16 %freeze to i32
19  ret i32 %zext
20}
21