xref: /llvm-project/llvm/test/CodeGen/RISCV/pr90652.ll (revision 2647bd73696ae987addd0e74774a44108accb1e6)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
3
4define i1 @test(i64 %x, i1 %cond1, i1 %cond2) {
5; CHECK-LABEL: test:
6; CHECK:       # %bb.0: # %entry
7; CHECK-NEXT:    addi a3, a0, 1
8; CHECK-NEXT:    slt a0, a3, a0
9; CHECK-NEXT:    not a1, a1
10; CHECK-NEXT:    and a0, a1, a0
11; CHECK-NEXT:    or a0, a2, a0
12; CHECK-NEXT:    ret
13entry:
14  %sadd = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %x, i64 1)
15  %ov = extractvalue { i64, i1 } %sadd, 1
16  %or = or i1 %cond2, %ov
17  %sel = select i1 %cond1, i1 %cond2, i1 %or
18  ret i1 %sel
19}
20