xref: /llvm-project/llvm/test/CodeGen/RISCV/pr66603.ll (revision 8505c3b15bfc535ff6624e71add4082680745187)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
2; RUN: llc < %s -mtriple=riscv32-- -mattr=+d -verify-machineinstrs | FileCheck %s -check-prefix=RV32
3; RUN: llc < %s -mtriple=riscv64-- -mattr=+d -verify-machineinstrs | FileCheck %s -check-prefix=RV64
4
5; Don't fold freeze(assertsext(x)) -> assertsext(freeze(x))
6define i32 @PR66603(double %x) nounwind {
7; RV32-LABEL: PR66603:
8; RV32:       # %bb.0:
9; RV32-NEXT:    fcvt.w.d a0, fa0, rtz
10; RV32-NEXT:    slli a0, a0, 24
11; RV32-NEXT:    srai a0, a0, 24
12; RV32-NEXT:    ret
13;
14; RV64-LABEL: PR66603:
15; RV64:       # %bb.0:
16; RV64-NEXT:    fcvt.l.d a0, fa0, rtz
17; RV64-NEXT:    slli a0, a0, 56
18; RV64-NEXT:    srai a0, a0, 56
19; RV64-NEXT:    ret
20  %as_i8 = fptosi double %x to i8
21  %frozen_i8 = freeze i8 %as_i8
22  %ext = sext i8 %frozen_i8 to i32
23  ret i32 %ext
24}
25