xref: /llvm-project/llvm/test/CodeGen/RISCV/pr64935.ll (revision d6639f83a98f29275d4ae490d2962c1ec1d298a5)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -mtriple=riscv32 < %s | FileCheck %s
3
4define i1 @f() {
5; CHECK-LABEL: f:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    lui a0, 524288
8; CHECK-NEXT:    not a0, a0
9; CHECK-NEXT:    sltiu a0, a0, 2
10; CHECK-NEXT:    xori a0, a0, 1
11; CHECK-NEXT:    ret
12  %B25 = shl i64 4294967296, -9223372036854775808
13  %B13 = sub i64 -1, -9223372036854775808
14  %C8 = icmp ugt i64 %B13, %B25
15  %B5 = sub i64 0, 4294967296 ; Don't remove this instruction!
16  ret i1 %C8
17}
18