xref: /llvm-project/llvm/test/CodeGen/RISCV/pr64772.ll (revision 846fbb06b8bf154a6c39d6b95a09b42ecd871811)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
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4define void @f() {
5; CHECK-LABEL: f:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    sb zero, 0(zero)
8; CHECK-NEXT:    ret
9  %B1 = shl i64 -9223372036854775808, 0
10  %LGV6 = load i8, ptr null, align 1
11  %G3 = getelementptr i32, ptr null, i64 %B1
12  %B5 = ashr i64 -9223372036854775808, 0
13  store i1 false, ptr %G3, align 1
14  store i8 1, ptr null, align 1
15  store i1 false, ptr null, align 1
16  ret void
17}
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