xref: /llvm-project/llvm/test/CodeGen/RISCV/pr64503.ll (revision e6b85c30276d8e35ed302b2defd7d17637d6edb3)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc < %s -mtriple=riscv32 | FileCheck %s
3
4define i1 @f(i64 %LGV1) {
5; CHECK-LABEL: f:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    li a0, 1
8; CHECK-NEXT:    ret
9  %B1 = xor i64 %LGV1, %LGV1
10  %B2 = srem i64 1, %B1
11  %B5 = lshr i64 1, %B2
12  %C4 = icmp ule i64 %LGV1, %B5
13  ret i1 %C4
14}
15
16define i64 @g(ptr %A, i64 %0) {
17; CHECK-LABEL: g:
18; CHECK:       # %bb.0:
19; CHECK-NEXT:    li a0, 1
20; CHECK-NEXT:    sb a0, 0(zero)
21; CHECK-NEXT:    ret
22  store i64 poison, ptr %A, align 4
23  %LGV1 = load i64, ptr %A, align 4
24  %B1 = ashr i64 1, %LGV1
25  %C = icmp sle i64 %0, %B1
26  store i1 %C, ptr null, align 1
27  ret i64 %LGV1
28}
29