1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv64 < %s | FileCheck --check-prefix=RV64I %s 3; RUN: llc -mtriple=riscv32 < %s | FileCheck --check-prefix=RV32I %s 4@var = external global i32 5 6define void @func() { 7; RV64I-LABEL: func: 8; RV64I: # %bb.0: 9; RV64I-NEXT: lui a0, 1 10; RV64I-NEXT: addiw a0, a0, 16 11; RV64I-NEXT: sub sp, sp, a0 12; RV64I-NEXT: .cfi_def_cfa_offset 4112 13; RV64I-NEXT: lui a0, %hi(var) 14; RV64I-NEXT: lw a1, %lo(var)(a0) 15; RV64I-NEXT: lw a2, %lo(var)(a0) 16; RV64I-NEXT: lw a3, %lo(var)(a0) 17; RV64I-NEXT: lw a4, %lo(var)(a0) 18; RV64I-NEXT: lw a5, %lo(var)(a0) 19; RV64I-NEXT: lw a6, %lo(var)(a0) 20; RV64I-NEXT: lw a7, %lo(var)(a0) 21; RV64I-NEXT: lw t0, %lo(var)(a0) 22; RV64I-NEXT: lw t1, %lo(var)(a0) 23; RV64I-NEXT: lw t2, %lo(var)(a0) 24; RV64I-NEXT: lw t3, %lo(var)(a0) 25; RV64I-NEXT: lw t4, %lo(var)(a0) 26; RV64I-NEXT: lw t5, %lo(var)(a0) 27; RV64I-NEXT: lw t6, %lo(var)(a0) 28; RV64I-NEXT: sd s0, 0(sp) 29; RV64I-NEXT: lui s0, 1 30; RV64I-NEXT: add s0, sp, s0 31; RV64I-NEXT: sw a1, 12(s0) 32; RV64I-NEXT: ld s0, 0(sp) 33; RV64I-NEXT: sw a1, %lo(var)(a0) 34; RV64I-NEXT: sw a2, %lo(var)(a0) 35; RV64I-NEXT: sw a3, %lo(var)(a0) 36; RV64I-NEXT: sw a4, %lo(var)(a0) 37; RV64I-NEXT: sw a5, %lo(var)(a0) 38; RV64I-NEXT: sw a6, %lo(var)(a0) 39; RV64I-NEXT: sw a7, %lo(var)(a0) 40; RV64I-NEXT: sw t0, %lo(var)(a0) 41; RV64I-NEXT: sw t1, %lo(var)(a0) 42; RV64I-NEXT: sw t2, %lo(var)(a0) 43; RV64I-NEXT: sw t3, %lo(var)(a0) 44; RV64I-NEXT: sw t4, %lo(var)(a0) 45; RV64I-NEXT: sw t5, %lo(var)(a0) 46; RV64I-NEXT: sw t6, %lo(var)(a0) 47; RV64I-NEXT: lui a0, 1 48; RV64I-NEXT: addiw a0, a0, 16 49; RV64I-NEXT: add sp, sp, a0 50; RV64I-NEXT: .cfi_def_cfa_offset 0 51; RV64I-NEXT: ret 52; 53; RV32I-LABEL: func: 54; RV32I: # %bb.0: 55; RV32I-NEXT: lui a0, 1 56; RV32I-NEXT: addi a0, a0, 16 57; RV32I-NEXT: sub sp, sp, a0 58; RV32I-NEXT: .cfi_def_cfa_offset 4112 59; RV32I-NEXT: lui a0, %hi(var) 60; RV32I-NEXT: lw a1, %lo(var)(a0) 61; RV32I-NEXT: lw a2, %lo(var)(a0) 62; RV32I-NEXT: lw a3, %lo(var)(a0) 63; RV32I-NEXT: lw a4, %lo(var)(a0) 64; RV32I-NEXT: lw a5, %lo(var)(a0) 65; RV32I-NEXT: lw a6, %lo(var)(a0) 66; RV32I-NEXT: lw a7, %lo(var)(a0) 67; RV32I-NEXT: lw t0, %lo(var)(a0) 68; RV32I-NEXT: lw t1, %lo(var)(a0) 69; RV32I-NEXT: lw t2, %lo(var)(a0) 70; RV32I-NEXT: lw t3, %lo(var)(a0) 71; RV32I-NEXT: lw t4, %lo(var)(a0) 72; RV32I-NEXT: lw t5, %lo(var)(a0) 73; RV32I-NEXT: lw t6, %lo(var)(a0) 74; RV32I-NEXT: sw s0, 0(sp) 75; RV32I-NEXT: lui s0, 1 76; RV32I-NEXT: add s0, sp, s0 77; RV32I-NEXT: sw a1, 12(s0) 78; RV32I-NEXT: lw s0, 0(sp) 79; RV32I-NEXT: sw a1, %lo(var)(a0) 80; RV32I-NEXT: sw a2, %lo(var)(a0) 81; RV32I-NEXT: sw a3, %lo(var)(a0) 82; RV32I-NEXT: sw a4, %lo(var)(a0) 83; RV32I-NEXT: sw a5, %lo(var)(a0) 84; RV32I-NEXT: sw a6, %lo(var)(a0) 85; RV32I-NEXT: sw a7, %lo(var)(a0) 86; RV32I-NEXT: sw t0, %lo(var)(a0) 87; RV32I-NEXT: sw t1, %lo(var)(a0) 88; RV32I-NEXT: sw t2, %lo(var)(a0) 89; RV32I-NEXT: sw t3, %lo(var)(a0) 90; RV32I-NEXT: sw t4, %lo(var)(a0) 91; RV32I-NEXT: sw t5, %lo(var)(a0) 92; RV32I-NEXT: sw t6, %lo(var)(a0) 93; RV32I-NEXT: lui a0, 1 94; RV32I-NEXT: addi a0, a0, 16 95; RV32I-NEXT: add sp, sp, a0 96; RV32I-NEXT: .cfi_def_cfa_offset 0 97; RV32I-NEXT: ret 98 %space = alloca i32, align 4 99 %stackspace = alloca[1024 x i32], align 4 100 101 ;; Load values to increase register pressure. 102 %v0 = load volatile i32, ptr @var 103 %v1 = load volatile i32, ptr @var 104 %v2 = load volatile i32, ptr @var 105 %v3 = load volatile i32, ptr @var 106 %v4 = load volatile i32, ptr @var 107 %v5 = load volatile i32, ptr @var 108 %v6 = load volatile i32, ptr @var 109 %v7 = load volatile i32, ptr @var 110 %v8 = load volatile i32, ptr @var 111 %v9 = load volatile i32, ptr @var 112 %v10 = load volatile i32, ptr @var 113 %v11 = load volatile i32, ptr @var 114 %v12 = load volatile i32, ptr @var 115 %v13 = load volatile i32, ptr @var 116 117 store volatile i32 %v0, ptr %space 118 119 ;; store values so they are used. 120 store volatile i32 %v0, ptr @var 121 store volatile i32 %v1, ptr @var 122 store volatile i32 %v2, ptr @var 123 store volatile i32 %v3, ptr @var 124 store volatile i32 %v4, ptr @var 125 store volatile i32 %v5, ptr @var 126 store volatile i32 %v6, ptr @var 127 store volatile i32 %v7, ptr @var 128 store volatile i32 %v8, ptr @var 129 store volatile i32 %v9, ptr @var 130 store volatile i32 %v10, ptr @var 131 store volatile i32 %v11, ptr @var 132 store volatile i32 %v12, ptr @var 133 store volatile i32 %v13, ptr @var 134 135 ret void 136} 137 138define void @shrink_wrap(i1 %c) { 139; RV64I-LABEL: shrink_wrap: 140; RV64I: # %bb.0: 141; RV64I-NEXT: andi a0, a0, 1 142; RV64I-NEXT: bnez a0, .LBB1_2 143; RV64I-NEXT: # %bb.1: # %bar 144; RV64I-NEXT: lui a0, 1 145; RV64I-NEXT: addiw a0, a0, 16 146; RV64I-NEXT: sub sp, sp, a0 147; RV64I-NEXT: .cfi_def_cfa_offset 4112 148; RV64I-NEXT: lui a0, %hi(var) 149; RV64I-NEXT: lw a1, %lo(var)(a0) 150; RV64I-NEXT: lw a2, %lo(var)(a0) 151; RV64I-NEXT: lw a3, %lo(var)(a0) 152; RV64I-NEXT: lw a4, %lo(var)(a0) 153; RV64I-NEXT: lw a5, %lo(var)(a0) 154; RV64I-NEXT: lw a6, %lo(var)(a0) 155; RV64I-NEXT: lw a7, %lo(var)(a0) 156; RV64I-NEXT: lw t0, %lo(var)(a0) 157; RV64I-NEXT: lw t1, %lo(var)(a0) 158; RV64I-NEXT: lw t2, %lo(var)(a0) 159; RV64I-NEXT: lw t3, %lo(var)(a0) 160; RV64I-NEXT: lw t4, %lo(var)(a0) 161; RV64I-NEXT: lw t5, %lo(var)(a0) 162; RV64I-NEXT: lw t6, %lo(var)(a0) 163; RV64I-NEXT: sd s0, 0(sp) 164; RV64I-NEXT: lui s0, 1 165; RV64I-NEXT: add s0, sp, s0 166; RV64I-NEXT: sw a1, 12(s0) 167; RV64I-NEXT: ld s0, 0(sp) 168; RV64I-NEXT: sw a1, %lo(var)(a0) 169; RV64I-NEXT: sw a2, %lo(var)(a0) 170; RV64I-NEXT: sw a3, %lo(var)(a0) 171; RV64I-NEXT: sw a4, %lo(var)(a0) 172; RV64I-NEXT: sw a5, %lo(var)(a0) 173; RV64I-NEXT: sw a6, %lo(var)(a0) 174; RV64I-NEXT: sw a7, %lo(var)(a0) 175; RV64I-NEXT: sw t0, %lo(var)(a0) 176; RV64I-NEXT: sw t1, %lo(var)(a0) 177; RV64I-NEXT: sw t2, %lo(var)(a0) 178; RV64I-NEXT: sw t3, %lo(var)(a0) 179; RV64I-NEXT: sw t4, %lo(var)(a0) 180; RV64I-NEXT: sw t5, %lo(var)(a0) 181; RV64I-NEXT: sw t6, %lo(var)(a0) 182; RV64I-NEXT: lui a0, 1 183; RV64I-NEXT: addiw a0, a0, 16 184; RV64I-NEXT: add sp, sp, a0 185; RV64I-NEXT: .cfi_def_cfa_offset 0 186; RV64I-NEXT: .LBB1_2: # %foo 187; RV64I-NEXT: ret 188; 189; RV32I-LABEL: shrink_wrap: 190; RV32I: # %bb.0: 191; RV32I-NEXT: andi a0, a0, 1 192; RV32I-NEXT: bnez a0, .LBB1_2 193; RV32I-NEXT: # %bb.1: # %bar 194; RV32I-NEXT: lui a0, 1 195; RV32I-NEXT: addi a0, a0, 16 196; RV32I-NEXT: sub sp, sp, a0 197; RV32I-NEXT: .cfi_def_cfa_offset 4112 198; RV32I-NEXT: lui a0, %hi(var) 199; RV32I-NEXT: lw a1, %lo(var)(a0) 200; RV32I-NEXT: lw a2, %lo(var)(a0) 201; RV32I-NEXT: lw a3, %lo(var)(a0) 202; RV32I-NEXT: lw a4, %lo(var)(a0) 203; RV32I-NEXT: lw a5, %lo(var)(a0) 204; RV32I-NEXT: lw a6, %lo(var)(a0) 205; RV32I-NEXT: lw a7, %lo(var)(a0) 206; RV32I-NEXT: lw t0, %lo(var)(a0) 207; RV32I-NEXT: lw t1, %lo(var)(a0) 208; RV32I-NEXT: lw t2, %lo(var)(a0) 209; RV32I-NEXT: lw t3, %lo(var)(a0) 210; RV32I-NEXT: lw t4, %lo(var)(a0) 211; RV32I-NEXT: lw t5, %lo(var)(a0) 212; RV32I-NEXT: lw t6, %lo(var)(a0) 213; RV32I-NEXT: sw s0, 0(sp) 214; RV32I-NEXT: lui s0, 1 215; RV32I-NEXT: add s0, sp, s0 216; RV32I-NEXT: sw a1, 12(s0) 217; RV32I-NEXT: lw s0, 0(sp) 218; RV32I-NEXT: sw a1, %lo(var)(a0) 219; RV32I-NEXT: sw a2, %lo(var)(a0) 220; RV32I-NEXT: sw a3, %lo(var)(a0) 221; RV32I-NEXT: sw a4, %lo(var)(a0) 222; RV32I-NEXT: sw a5, %lo(var)(a0) 223; RV32I-NEXT: sw a6, %lo(var)(a0) 224; RV32I-NEXT: sw a7, %lo(var)(a0) 225; RV32I-NEXT: sw t0, %lo(var)(a0) 226; RV32I-NEXT: sw t1, %lo(var)(a0) 227; RV32I-NEXT: sw t2, %lo(var)(a0) 228; RV32I-NEXT: sw t3, %lo(var)(a0) 229; RV32I-NEXT: sw t4, %lo(var)(a0) 230; RV32I-NEXT: sw t5, %lo(var)(a0) 231; RV32I-NEXT: sw t6, %lo(var)(a0) 232; RV32I-NEXT: lui a0, 1 233; RV32I-NEXT: addi a0, a0, 16 234; RV32I-NEXT: add sp, sp, a0 235; RV32I-NEXT: .cfi_def_cfa_offset 0 236; RV32I-NEXT: .LBB1_2: # %foo 237; RV32I-NEXT: ret 238 %space = alloca i32, align 4 239 %stackspace = alloca[1024 x i32], align 4 240 br i1 %c, label %foo, label %bar 241 242bar: 243 244 ;; Load values to increase register pressure. 245 %v0 = load volatile i32, ptr @var 246 %v1 = load volatile i32, ptr @var 247 %v2 = load volatile i32, ptr @var 248 %v3 = load volatile i32, ptr @var 249 %v4 = load volatile i32, ptr @var 250 %v5 = load volatile i32, ptr @var 251 %v6 = load volatile i32, ptr @var 252 %v7 = load volatile i32, ptr @var 253 %v8 = load volatile i32, ptr @var 254 %v9 = load volatile i32, ptr @var 255 %v10 = load volatile i32, ptr @var 256 %v11 = load volatile i32, ptr @var 257 %v12 = load volatile i32, ptr @var 258 %v13 = load volatile i32, ptr @var 259 260 store volatile i32 %v0, ptr %space 261 262 ;; store values so they are used. 263 store volatile i32 %v0, ptr @var 264 store volatile i32 %v1, ptr @var 265 store volatile i32 %v2, ptr @var 266 store volatile i32 %v3, ptr @var 267 store volatile i32 %v4, ptr @var 268 store volatile i32 %v5, ptr @var 269 store volatile i32 %v6, ptr @var 270 store volatile i32 %v7, ptr @var 271 store volatile i32 %v8, ptr @var 272 store volatile i32 %v9, ptr @var 273 store volatile i32 %v10, ptr @var 274 store volatile i32 %v11, ptr @var 275 store volatile i32 %v12, ptr @var 276 store volatile i32 %v13, ptr @var 277 br label %foo 278 279foo: 280 ret void 281} 282