xref: /llvm-project/llvm/test/CodeGen/RISCV/pr56457.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s
3
4declare i15 @llvm.ctlz.i15(i15, i1)
5
6define i15 @foo(i15 %x) nounwind {
7; CHECK-LABEL: foo:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    slli a1, a0, 49
10; CHECK-NEXT:    beqz a1, .LBB0_2
11; CHECK-NEXT:  # %bb.1: # %cond.false
12; CHECK-NEXT:    srli a1, a1, 50
13; CHECK-NEXT:    lui a2, 1
14; CHECK-NEXT:    lui a3, 209715
15; CHECK-NEXT:    lui a4, 61681
16; CHECK-NEXT:    or a0, a0, a1
17; CHECK-NEXT:    addiw a1, a2, 1365
18; CHECK-NEXT:    addiw a2, a3, 819
19; CHECK-NEXT:    addiw a3, a4, -241
20; CHECK-NEXT:    slli a4, a2, 32
21; CHECK-NEXT:    add a2, a2, a4
22; CHECK-NEXT:    slli a4, a3, 32
23; CHECK-NEXT:    add a3, a3, a4
24; CHECK-NEXT:    slli a4, a0, 49
25; CHECK-NEXT:    srli a4, a4, 51
26; CHECK-NEXT:    or a0, a0, a4
27; CHECK-NEXT:    slli a4, a0, 49
28; CHECK-NEXT:    srli a4, a4, 53
29; CHECK-NEXT:    or a0, a0, a4
30; CHECK-NEXT:    slli a4, a0, 49
31; CHECK-NEXT:    srli a4, a4, 57
32; CHECK-NEXT:    or a0, a0, a4
33; CHECK-NEXT:    not a0, a0
34; CHECK-NEXT:    srli a4, a0, 1
35; CHECK-NEXT:    and a1, a4, a1
36; CHECK-NEXT:    slli a0, a0, 49
37; CHECK-NEXT:    srli a0, a0, 49
38; CHECK-NEXT:    sub a0, a0, a1
39; CHECK-NEXT:    and a1, a0, a2
40; CHECK-NEXT:    srli a0, a0, 2
41; CHECK-NEXT:    and a0, a0, a2
42; CHECK-NEXT:    add a0, a1, a0
43; CHECK-NEXT:    srli a1, a0, 4
44; CHECK-NEXT:    add a0, a0, a1
45; CHECK-NEXT:    lui a1, 4112
46; CHECK-NEXT:    addiw a1, a1, 257
47; CHECK-NEXT:    and a0, a0, a3
48; CHECK-NEXT:    slli a2, a1, 32
49; CHECK-NEXT:    add a1, a1, a2
50; CHECK-NEXT:    mul a0, a0, a1
51; CHECK-NEXT:    srli a0, a0, 56
52; CHECK-NEXT:    ret
53; CHECK-NEXT:  .LBB0_2:
54; CHECK-NEXT:    li a0, 15
55; CHECK-NEXT:    ret
56  %a = call i15 @llvm.ctlz.i15(i15 %x, i1 false)
57  ret i15 %a
58}
59