xref: /llvm-project/llvm/test/CodeGen/RISCV/pr56110.ll (revision 9067070d91e9d8cdd8509ffa56a076f08a3d7281)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=riscv32 | FileCheck %s
3; RUN: llc < %s -mtriple=riscv32 -mattr=+unaligned-scalar-mem | FileCheck %s
4
5define void @foo_set(ptr nocapture noundef %a, i32 noundef %v) {
6; CHECK-LABEL: foo_set:
7; CHECK:       # %bb.0: # %entry
8; CHECK-NEXT:    srli a2, a1, 8
9; CHECK-NEXT:    sb a1, 3(a0)
10; CHECK-NEXT:    sb a2, 4(a0)
11; CHECK-NEXT:    ret
12entry:
13  %bf.load = load i96, ptr %a, align 1
14  %0 = and i32 %v, 65535
15  %bf.value = zext i32 %0 to i96
16  %bf.shl = shl nuw nsw i96 %bf.value, 24
17  %bf.clear = and i96 %bf.load, -1099494850561
18  %bf.set = or i96 %bf.clear, %bf.shl
19  store i96 %bf.set, ptr %a, align 1
20  ret void
21}
22