xref: /llvm-project/llvm/test/CodeGen/RISCV/pr55201.ll (revision 6affe87bda203b6d6538f41bb44879509962c695)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb | FileCheck %s
3
4define i32 @f(i32 %x) {
5; CHECK-LABEL: f:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    rori a0, a0, 27
8; CHECK-NEXT:    ori a0, a0, 32
9; CHECK-NEXT:    andi a0, a0, -31
10; CHECK-NEXT:    ret
11  %or1 = or i32 %x, 1
12  %sh1 = shl i32 %or1, 5
13  %sh2 = lshr i32 %x, 27
14  %1 = and i32 %sh2, 1
15  %r = or i32 %sh1, %1
16  ret i32 %r
17}
18