xref: /llvm-project/llvm/test/CodeGen/RISCV/pr51206.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2;RUN: llc < %s -mtriple=riscv64-unknown-linux-gnu -mattr=+m | FileCheck %s
3
4; This test used to cause an infinite loop.
5
6@global = global i8 0, align 1
7@global.1 = global i32 0, align 4
8@global.2 = global i8 0, align 1
9@global.3 = global i32 0, align 4
10
11define signext i32 @wobble() nounwind {
12; CHECK-LABEL: wobble:
13; CHECK:       # %bb.0: # %bb
14; CHECK-NEXT:    lui a0, %hi(global)
15; CHECK-NEXT:    lui a1, %hi(global.1)
16; CHECK-NEXT:    lbu a0, %lo(global)(a0)
17; CHECK-NEXT:    lui a2, %hi(global.2)
18; CHECK-NEXT:    lui a3, 52429
19; CHECK-NEXT:    lbu a2, %lo(global.2)(a2)
20; CHECK-NEXT:    addi a0, a0, 1
21; CHECK-NEXT:    sw a0, %lo(global.1)(a1)
22; CHECK-NEXT:    lui a1, %hi(global.3)
23; CHECK-NEXT:    slli a3, a3, 4
24; CHECK-NEXT:    mul a0, a0, a2
25; CHECK-NEXT:    slli a2, a0, 48
26; CHECK-NEXT:    mulhu a2, a2, a3
27; CHECK-NEXT:    srli a2, a2, 18
28; CHECK-NEXT:    li a3, 5
29; CHECK-NEXT:    sw a2, %lo(global.3)(a1)
30; CHECK-NEXT:    bgeu a0, a3, .LBB0_2
31; CHECK-NEXT:  # %bb.1: # %bb12
32; CHECK-NEXT:    li a0, 0
33; CHECK-NEXT:    ret
34; CHECK-NEXT:  .LBB0_2: # %bb10
35; CHECK-NEXT:    tail quux
36bb:
37  %tmp = load i8, ptr @global, align 1
38  %tmp1 = zext i8 %tmp to i32
39  %tmp2 = add nuw nsw i32 %tmp1, 1
40  store i32 %tmp2, ptr @global.1, align 4
41  %tmp3 = load i8, ptr @global.2, align 1
42  %tmp4 = zext i8 %tmp3 to i32
43  %tmp5 = mul nuw nsw i32 %tmp2, %tmp4
44  %tmp6 = trunc i32 %tmp5 to i16
45  %tmp7 = udiv i16 %tmp6, 5
46  %tmp8 = zext i16 %tmp7 to i32
47  store i32 %tmp8, ptr @global.3, align 4
48  %tmp9 = icmp ult i32 %tmp5, 5
49  br i1 %tmp9, label %bb12, label %bb10
50
51bb10:                                             ; preds = %bb
52  %tmp11 = tail call signext i32 @quux()
53  br label %bb12
54
55bb12:                                             ; preds = %bb10, %bb
56  ret i32 undef
57}
58
59declare signext i32 @quux(...)
60