1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I 4; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \ 5; RUN: | FileCheck %s -check-prefixes=CHECK,RV32ZBB 6 7define i32 @orc_b_i32_mul255(i32 %x) nounwind { 8; RV32I-LABEL: orc_b_i32_mul255: 9; RV32I: # %bb.0: # %entry 10; RV32I-NEXT: lui a1, 4112 11; RV32I-NEXT: addi a1, a1, 257 12; RV32I-NEXT: and a0, a0, a1 13; RV32I-NEXT: slli a1, a0, 8 14; RV32I-NEXT: sub a0, a1, a0 15; RV32I-NEXT: ret 16; 17; RV32ZBB-LABEL: orc_b_i32_mul255: 18; RV32ZBB: # %bb.0: # %entry 19; RV32ZBB-NEXT: lui a1, 4112 20; RV32ZBB-NEXT: addi a1, a1, 257 21; RV32ZBB-NEXT: and a0, a0, a1 22; RV32ZBB-NEXT: orc.b a0, a0 23; RV32ZBB-NEXT: ret 24entry: 25 %and = and i32 %x, 16843009 26 %mul = mul nuw nsw i32 %and, 255 27 ret i32 %mul 28} 29 30 31define i32 @orc_b_i32_sub_shl8x_x_lsb(i32 %x) { 32; RV32I-LABEL: orc_b_i32_sub_shl8x_x_lsb: 33; RV32I: # %bb.0: # %entry 34; RV32I-NEXT: lui a1, 4112 35; RV32I-NEXT: addi a1, a1, 257 36; RV32I-NEXT: and a0, a0, a1 37; RV32I-NEXT: slli a1, a0, 8 38; RV32I-NEXT: sub a0, a1, a0 39; RV32I-NEXT: ret 40; 41; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_lsb: 42; RV32ZBB: # %bb.0: # %entry 43; RV32ZBB-NEXT: lui a1, 4112 44; RV32ZBB-NEXT: addi a1, a1, 257 45; RV32ZBB-NEXT: and a0, a0, a1 46; RV32ZBB-NEXT: orc.b a0, a0 47; RV32ZBB-NEXT: ret 48entry: 49 %and = and i32 %x, 16843009 50 %sub = mul nuw i32 %and, 255 51 ret i32 %sub 52} 53 54define i32 @orc_b_i32_sub_shl8x_x_lsb_preshifted(i32 %x){ 55; RV32I-LABEL: orc_b_i32_sub_shl8x_x_lsb_preshifted: 56; RV32I: # %bb.0: # %entry 57; RV32I-NEXT: srli a0, a0, 11 58; RV32I-NEXT: lui a1, 16 59; RV32I-NEXT: addi a1, a1, 257 60; RV32I-NEXT: and a0, a0, a1 61; RV32I-NEXT: slli a1, a0, 8 62; RV32I-NEXT: sub a0, a1, a0 63; RV32I-NEXT: ret 64; 65; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_lsb_preshifted: 66; RV32ZBB: # %bb.0: # %entry 67; RV32ZBB-NEXT: srli a0, a0, 11 68; RV32ZBB-NEXT: lui a1, 16 69; RV32ZBB-NEXT: addi a1, a1, 257 70; RV32ZBB-NEXT: and a0, a0, a1 71; RV32ZBB-NEXT: orc.b a0, a0 72; RV32ZBB-NEXT: ret 73entry: 74 %shr = lshr i32 %x, 11 75 %and = and i32 %shr, 16843009 76 %sub = mul nuw i32 %and, 255 77 ret i32 %sub 78} 79 80 81define i32 @orc_b_i32_sub_shl8x_x_b1(i32 %x) { 82; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b1: 83; RV32I: # %bb.0: # %entry 84; RV32I-NEXT: lui a1, 8224 85; RV32I-NEXT: addi a1, a1, 514 86; RV32I-NEXT: and a0, a0, a1 87; RV32I-NEXT: slli a1, a0, 7 88; RV32I-NEXT: srli a0, a0, 1 89; RV32I-NEXT: sub a0, a1, a0 90; RV32I-NEXT: ret 91; 92; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1: 93; RV32ZBB: # %bb.0: # %entry 94; RV32ZBB-NEXT: lui a1, 8224 95; RV32ZBB-NEXT: addi a1, a1, 514 96; RV32ZBB-NEXT: and a0, a0, a1 97; RV32ZBB-NEXT: orc.b a0, a0 98; RV32ZBB-NEXT: ret 99entry: 100 %and = and i32 %x, 33686018 101 %shl = shl i32 %and, 7 102 %shr = lshr exact i32 %and, 1 103 %sub = sub nsw i32 %shl, %shr 104 ret i32 %sub 105} 106 107 108define i32 @orc_b_i32_sub_shl8x_x_b2(i32 %x) { 109; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b2: 110; RV32I: # %bb.0: # %entry 111; RV32I-NEXT: lui a1, 16448 112; RV32I-NEXT: addi a1, a1, 1028 113; RV32I-NEXT: and a0, a0, a1 114; RV32I-NEXT: slli a1, a0, 6 115; RV32I-NEXT: srli a0, a0, 2 116; RV32I-NEXT: sub a0, a1, a0 117; RV32I-NEXT: ret 118; 119; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b2: 120; RV32ZBB: # %bb.0: # %entry 121; RV32ZBB-NEXT: lui a1, 16448 122; RV32ZBB-NEXT: addi a1, a1, 1028 123; RV32ZBB-NEXT: and a0, a0, a1 124; RV32ZBB-NEXT: orc.b a0, a0 125; RV32ZBB-NEXT: ret 126entry: 127 %and = and i32 %x, 67372036 128 %shl = shl i32 %and, 6 129 %shr = lshr exact i32 %and, 2 130 %sub = sub nsw i32 %shl, %shr 131 ret i32 %sub 132} 133 134 135define i32 @orc_b_i32_sub_shl8x_x_b3(i32 %x) { 136; CHECK-LABEL: orc_b_i32_sub_shl8x_x_b3: 137; CHECK: # %bb.0: # %entry 138; CHECK-NEXT: lui a1, 24672 139; CHECK-NEXT: addi a1, a1, 1542 140; CHECK-NEXT: and a0, a0, a1 141; CHECK-NEXT: slli a1, a0, 5 142; CHECK-NEXT: srli a0, a0, 3 143; CHECK-NEXT: sub a0, a1, a0 144; CHECK-NEXT: ret 145entry: 146 %and = and i32 %x, 101058054 147 %shl = shl nuw i32 %and, 5 148 %shr = lshr i32 %and, 3 149 %sub = sub nsw i32 %shl, %shr 150 ret i32 %sub 151} 152 153 154define i32 @orc_b_i32_sub_shl8x_x_b4(i32 %x) { 155; CHECK-LABEL: orc_b_i32_sub_shl8x_x_b4: 156; CHECK: # %bb.0: # %entry 157; CHECK-NEXT: lui a1, 32897 158; CHECK-NEXT: addi a1, a1, -2040 159; CHECK-NEXT: and a0, a0, a1 160; CHECK-NEXT: slli a1, a0, 4 161; CHECK-NEXT: srli a0, a0, 4 162; CHECK-NEXT: sub a0, a1, a0 163; CHECK-NEXT: ret 164entry: 165 %and = and i32 %x, 134744072 166 %shl = shl nuw i32 %and, 4 167 %shr = lshr i32 %and, 4 168 %sub = sub nsw i32 %shl, %shr 169 ret i32 %sub 170} 171 172 173define i32 @orc_b_i32_sub_shl8x_x_b5(i32 %x) { 174; CHECK-LABEL: orc_b_i32_sub_shl8x_x_b5: 175; CHECK: # %bb.0: # %entry 176; CHECK-NEXT: lui a1, 65793 177; CHECK-NEXT: addi a1, a1, 16 178; CHECK-NEXT: and a0, a0, a1 179; CHECK-NEXT: slli a1, a0, 3 180; CHECK-NEXT: srli a0, a0, 5 181; CHECK-NEXT: sub a0, a1, a0 182; CHECK-NEXT: ret 183entry: 184 %and = and i32 %x, 269488144 185 %shl = shl nuw i32 %and, 3 186 %shr = lshr i32 %and, 5 187 %sub = sub nsw i32 %shl, %shr 188 ret i32 %sub 189} 190 191 192define i32 @orc_b_i32_sub_shl8x_x_b6(i32 %x) { 193; CHECK-LABEL: orc_b_i32_sub_shl8x_x_b6: 194; CHECK: # %bb.0: # %entry 195; CHECK-NEXT: lui a1, 131586 196; CHECK-NEXT: addi a1, a1, 32 197; CHECK-NEXT: and a0, a0, a1 198; CHECK-NEXT: slli a1, a0, 2 199; CHECK-NEXT: srli a0, a0, 6 200; CHECK-NEXT: sub a0, a1, a0 201; CHECK-NEXT: ret 202entry: 203 %and = and i32 %x, 538976288 204 %shl = shl nuw i32 %and, 2 205 %shr = lshr i32 %and, 6 206 %sub = sub nsw i32 %shl, %shr 207 ret i32 %sub 208} 209 210 211define i32 @orc_b_i32_sub_shl8x_x_b7(i32 %x) { 212; CHECK-LABEL: orc_b_i32_sub_shl8x_x_b7: 213; CHECK: # %bb.0: # %entry 214; CHECK-NEXT: lui a1, 263172 215; CHECK-NEXT: addi a1, a1, 64 216; CHECK-NEXT: and a0, a0, a1 217; CHECK-NEXT: slli a1, a0, 1 218; CHECK-NEXT: srli a0, a0, 7 219; CHECK-NEXT: sub a0, a1, a0 220; CHECK-NEXT: ret 221entry: 222 %and = and i32 %x, 1077952576 223 %shl = shl nuw i32 %and, 1 224 %shr = lshr i32 %and, 7 225 %sub = sub nsw i32 %shl, %shr 226 ret i32 %sub 227} 228 229define i32 @orc_b_i32_sub_shl8x_x_b1_shl_used(i32 %x, ptr %arr) { 230; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b1_shl_used: 231; RV32I: # %bb.0: # %entry 232; RV32I-NEXT: lui a2, 8224 233; RV32I-NEXT: addi a2, a2, 514 234; RV32I-NEXT: and a0, a0, a2 235; RV32I-NEXT: slli a2, a0, 7 236; RV32I-NEXT: srli a3, a0, 1 237; RV32I-NEXT: sub a0, a2, a3 238; RV32I-NEXT: sw a3, 0(a1) 239; RV32I-NEXT: ret 240; 241; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1_shl_used: 242; RV32ZBB: # %bb.0: # %entry 243; RV32ZBB-NEXT: lui a2, 8224 244; RV32ZBB-NEXT: addi a2, a2, 514 245; RV32ZBB-NEXT: and a0, a0, a2 246; RV32ZBB-NEXT: srli a2, a0, 1 247; RV32ZBB-NEXT: orc.b a0, a0 248; RV32ZBB-NEXT: sw a2, 0(a1) 249; RV32ZBB-NEXT: ret 250entry: 251 %and = and i32 %x, 33686018 252 %shl = shl i32 %and, 7 253 %shr = lshr exact i32 %and, 1 254 store i32 %shr, ptr %arr, align 4 255 %sub = sub nsw i32 %shl, %shr 256 ret i32 %sub 257} 258 259define i32 @orc_b_i32_sub_shl8x_x_b1_srl_used(i32 %x, ptr %arr) { 260; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b1_srl_used: 261; RV32I: # %bb.0: # %entry 262; RV32I-NEXT: lui a2, 8224 263; RV32I-NEXT: addi a2, a2, 514 264; RV32I-NEXT: and a0, a0, a2 265; RV32I-NEXT: slli a2, a0, 7 266; RV32I-NEXT: srli a0, a0, 1 267; RV32I-NEXT: sub a0, a2, a0 268; RV32I-NEXT: sw a2, 0(a1) 269; RV32I-NEXT: ret 270; 271; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1_srl_used: 272; RV32ZBB: # %bb.0: # %entry 273; RV32ZBB-NEXT: lui a2, 8224 274; RV32ZBB-NEXT: addi a2, a2, 514 275; RV32ZBB-NEXT: and a0, a0, a2 276; RV32ZBB-NEXT: slli a2, a0, 7 277; RV32ZBB-NEXT: orc.b a0, a0 278; RV32ZBB-NEXT: sw a2, 0(a1) 279; RV32ZBB-NEXT: ret 280entry: 281 %and = and i32 %x, 33686018 282 %shl = shl i32 %and, 7 283 %shr = lshr exact i32 %and, 1 284 store i32 %shl, ptr %arr, align 4 285 %sub = sub nsw i32 %shl, %shr 286 ret i32 %sub 287} 288 289 290define i32 @orc_b_i32_sub_shl8x_x_b1_not_used(i32 %x, ptr %arr) { 291; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b1_not_used: 292; RV32I: # %bb.0: # %entry 293; RV32I-NEXT: lui a1, 8224 294; RV32I-NEXT: addi a1, a1, 514 295; RV32I-NEXT: and a0, a0, a1 296; RV32I-NEXT: slli a1, a0, 7 297; RV32I-NEXT: srli a0, a0, 1 298; RV32I-NEXT: sub a0, a1, a0 299; RV32I-NEXT: ret 300; 301; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1_not_used: 302; RV32ZBB: # %bb.0: # %entry 303; RV32ZBB-NEXT: lui a1, 8224 304; RV32ZBB-NEXT: addi a1, a1, 514 305; RV32ZBB-NEXT: and a0, a0, a1 306; RV32ZBB-NEXT: orc.b a0, a0 307; RV32ZBB-NEXT: ret 308entry: 309 %and = and i32 %x, 33686018 310 %shl = shl i32 %and, 7 311 %shr = lshr exact i32 %and, 1 312 %sub = sub nsw i32 %shl, %shr 313 ret i32 %sub 314} 315 316define i32 @orc_b_i32_sub_shl8x_x_shl_used(i32 %x, ptr %arr){ 317; CHECK-LABEL: orc_b_i32_sub_shl8x_x_shl_used: 318; CHECK: # %bb.0: # %entry 319; CHECK-NEXT: lui a2, 4112 320; CHECK-NEXT: addi a2, a2, 257 321; CHECK-NEXT: and a0, a0, a2 322; CHECK-NEXT: slli a2, a0, 8 323; CHECK-NEXT: sub a0, a2, a0 324; CHECK-NEXT: sw a2, 0(a1) 325; CHECK-NEXT: ret 326entry: 327 %and = and i32 %x, 16843009 328 %shl = shl i32 %and, 8 329 store i32 %shl, ptr %arr, align 4 330 %sub = mul nuw i32 %and, 255 331 ret i32 %sub 332} 333 334define i32 @orc_b_i32_sub_shl8x_x_b1_both_used(i32 %x, ptr %arr) { 335; CHECK-LABEL: orc_b_i32_sub_shl8x_x_b1_both_used: 336; CHECK: # %bb.0: # %entry 337; CHECK-NEXT: lui a2, 8224 338; CHECK-NEXT: addi a2, a2, 514 339; CHECK-NEXT: and a0, a0, a2 340; CHECK-NEXT: slli a2, a0, 7 341; CHECK-NEXT: srli a3, a0, 1 342; CHECK-NEXT: sub a0, a2, a3 343; CHECK-NEXT: sw a2, 0(a1) 344; CHECK-NEXT: sw a3, 4(a1) 345; CHECK-NEXT: ret 346entry: 347 %and = and i32 %x, 33686018 348 %shl = shl i32 %and, 7 349 %shr = lshr exact i32 %and, 1 350 store i32 %shl, ptr %arr, align 4 351 %arrayidx1 = getelementptr inbounds i8, ptr %arr, i32 4 352 store i32 %shr, ptr %arrayidx1, align 4 353 %sub = sub nsw i32 %shl, %shr 354 ret i32 %sub 355} 356 357 358define i32 @orc_b_i32_sub_x_shr8x(i32 %x) { 359; CHECK-LABEL: orc_b_i32_sub_x_shr8x: 360; CHECK: # %bb.0: # %entry 361; CHECK-NEXT: lui a1, 4112 362; CHECK-NEXT: addi a1, a1, 257 363; CHECK-NEXT: and a0, a0, a1 364; CHECK-NEXT: srli a1, a0, 8 365; CHECK-NEXT: sub a0, a0, a1 366; CHECK-NEXT: ret 367entry: 368 %and = and i32 %x, 16843009 369 %shr = lshr i32 %and, 8 370 %sub = sub nsw i32 %and, %shr 371 ret i32 %sub 372} 373