xref: /llvm-project/llvm/test/CodeGen/RISCV/or-is-add.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32
3; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefixes=RV64
4
5define signext i32 @test1(i32 signext %x) {
6; RV32-LABEL: test1:
7; RV32:       # %bb.0:
8; RV32-NEXT:    slli a0, a0, 1
9; RV32-NEXT:    addi a0, a0, 1
10; RV32-NEXT:    ret
11;
12; RV64-LABEL: test1:
13; RV64:       # %bb.0:
14; RV64-NEXT:    slliw a0, a0, 1
15; RV64-NEXT:    addi a0, a0, 1
16; RV64-NEXT:    ret
17  %a = shl i32 %x, 1
18  %b = or i32 %a, 1
19  ret i32 %b
20}
21
22define i64 @test2(i64 %x) {
23; RV32-LABEL: test2:
24; RV32:       # %bb.0:
25; RV32-NEXT:    andi a0, a0, -4
26; RV32-NEXT:    addi a0, a0, 2
27; RV32-NEXT:    ret
28;
29; RV64-LABEL: test2:
30; RV64:       # %bb.0:
31; RV64-NEXT:    andi a0, a0, -4
32; RV64-NEXT:    addi a0, a0, 2
33; RV64-NEXT:    ret
34  %a = and i64 %x, -4
35  %b = or i64 %a, 2
36  ret i64 %b
37}
38
39define signext i32 @test3(i32 signext %x) {
40; RV32-LABEL: test3:
41; RV32:       # %bb.0:
42; RV32-NEXT:    slli a0, a0, 3
43; RV32-NEXT:    addi a0, a0, 6
44; RV32-NEXT:    ret
45;
46; RV64-LABEL: test3:
47; RV64:       # %bb.0:
48; RV64-NEXT:    slliw a0, a0, 3
49; RV64-NEXT:    addi a0, a0, 6
50; RV64-NEXT:    ret
51  %a = shl i32 %x, 3
52  %b = add i32 %a, 6
53  ret i32 %b
54}
55
56define i64 @test4(i64 %x) {
57; RV32-LABEL: test4:
58; RV32:       # %bb.0:
59; RV32-NEXT:    srli a2, a0, 28
60; RV32-NEXT:    slli a1, a1, 4
61; RV32-NEXT:    slli a0, a0, 4
62; RV32-NEXT:    or a1, a1, a2
63; RV32-NEXT:    addi a0, a0, 13
64; RV32-NEXT:    ret
65;
66; RV64-LABEL: test4:
67; RV64:       # %bb.0:
68; RV64-NEXT:    slli a0, a0, 4
69; RV64-NEXT:    addi a0, a0, 13
70; RV64-NEXT:    ret
71  %a = shl i64 %x, 4
72  %b = add i64 %a, 13
73  ret i64 %b
74}
75
76define signext i32 @test5(i32 signext %x) {
77; RV32-LABEL: test5:
78; RV32:       # %bb.0:
79; RV32-NEXT:    srli a0, a0, 24
80; RV32-NEXT:    addi a0, a0, 256
81; RV32-NEXT:    ret
82;
83; RV64-LABEL: test5:
84; RV64:       # %bb.0:
85; RV64-NEXT:    srliw a0, a0, 24
86; RV64-NEXT:    addi a0, a0, 256
87; RV64-NEXT:    ret
88  %a = lshr i32 %x, 24
89  %b = xor i32 %a, 256
90  ret i32 %b
91}
92
93define i64 @test6(i64 %x) {
94; RV32-LABEL: test6:
95; RV32:       # %bb.0:
96; RV32-NEXT:    srli a1, a1, 22
97; RV32-NEXT:    addi a0, a1, 1024
98; RV32-NEXT:    li a1, 0
99; RV32-NEXT:    ret
100;
101; RV64-LABEL: test6:
102; RV64:       # %bb.0:
103; RV64-NEXT:    srli a0, a0, 54
104; RV64-NEXT:    addi a0, a0, 1024
105; RV64-NEXT:    ret
106  %a = lshr i64 %x, 54
107  %b = xor i64 %a, 1024
108  ret i64 %b
109}
110
111define signext i32 @test7(i32 signext %x) {
112; RV32-LABEL: test7:
113; RV32:       # %bb.0:
114; RV32-NEXT:    addi a0, a0, 1
115; RV32-NEXT:    ret
116;
117; RV64-LABEL: test7:
118; RV64:       # %bb.0:
119; RV64-NEXT:    ori a0, a0, 1
120; RV64-NEXT:    ret
121  %a = or disjoint i32 %x, 1
122  ret i32 %a
123}
124