xref: /llvm-project/llvm/test/CodeGen/RISCV/nontemporal-scalable.ll (revision f808788487ab9db7da262a0b43483fb07bf6b50f) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -mtriple=riscv64 -mattr=+zihintntl,+f,+d,+zfh,+v < %s | FileCheck %s -check-prefix=CHECK-RV64V
3; RUN: llc -mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh,+v < %s | FileCheck %s -check-prefix=CHECK-RV32V
4
5define <vscale x 2 x i64> @test_nontemporal_load_nxv2i64(ptr %p) {
6; CHECK-RV64V-LABEL: test_nontemporal_load_nxv2i64:
7; CHECK-RV64V:       # %bb.0:
8; CHECK-RV64V-NEXT:    ntl.all
9; CHECK-RV64V-NEXT:    vl2re64.v v8, (a0)
10; CHECK-RV64V-NEXT:    ret
11;
12; CHECK-RV32V-LABEL: test_nontemporal_load_nxv2i64:
13; CHECK-RV32V:       # %bb.0:
14; CHECK-RV32V-NEXT:    ntl.all
15; CHECK-RV32V-NEXT:    vl2re64.v v8, (a0)
16; CHECK-RV32V-NEXT:    ret
17  %1 = load <vscale x 2 x i64>, ptr %p, !nontemporal !0
18  ret <vscale x 2 x i64> %1
19}
20
21define <vscale x 4 x i32> @test_nontemporal_load_nxv4i32(ptr %p) {
22; CHECK-RV64V-LABEL: test_nontemporal_load_nxv4i32:
23; CHECK-RV64V:       # %bb.0:
24; CHECK-RV64V-NEXT:    ntl.all
25; CHECK-RV64V-NEXT:    vl2re32.v v8, (a0)
26; CHECK-RV64V-NEXT:    ret
27;
28; CHECK-RV32V-LABEL: test_nontemporal_load_nxv4i32:
29; CHECK-RV32V:       # %bb.0:
30; CHECK-RV32V-NEXT:    ntl.all
31; CHECK-RV32V-NEXT:    vl2re32.v v8, (a0)
32; CHECK-RV32V-NEXT:    ret
33  %1 = load <vscale x 4 x i32>, ptr %p, !nontemporal !0
34  ret <vscale x 4 x i32> %1
35}
36
37define <vscale x 8 x i16> @test_nontemporal_load_nxv8i16(ptr %p) {
38; CHECK-RV64V-LABEL: test_nontemporal_load_nxv8i16:
39; CHECK-RV64V:       # %bb.0:
40; CHECK-RV64V-NEXT:    ntl.all
41; CHECK-RV64V-NEXT:    vl2re16.v v8, (a0)
42; CHECK-RV64V-NEXT:    ret
43;
44; CHECK-RV32V-LABEL: test_nontemporal_load_nxv8i16:
45; CHECK-RV32V:       # %bb.0:
46; CHECK-RV32V-NEXT:    ntl.all
47; CHECK-RV32V-NEXT:    vl2re16.v v8, (a0)
48; CHECK-RV32V-NEXT:    ret
49  %1 = load <vscale x 8 x i16>, ptr %p, !nontemporal !0
50  ret <vscale x 8 x i16> %1
51}
52
53define <vscale x 16 x i8> @test_nontemporal_load_nxv16i8(ptr %p) {
54; CHECK-RV64V-LABEL: test_nontemporal_load_nxv16i8:
55; CHECK-RV64V:       # %bb.0:
56; CHECK-RV64V-NEXT:    ntl.all
57; CHECK-RV64V-NEXT:    vl2r.v v8, (a0)
58; CHECK-RV64V-NEXT:    ret
59;
60; CHECK-RV32V-LABEL: test_nontemporal_load_nxv16i8:
61; CHECK-RV32V:       # %bb.0:
62; CHECK-RV32V-NEXT:    ntl.all
63; CHECK-RV32V-NEXT:    vl2r.v v8, (a0)
64; CHECK-RV32V-NEXT:    ret
65  %1 = load <vscale x 16 x i8>, ptr %p, !nontemporal !0
66  ret <vscale x 16 x i8> %1
67}
68
69define void @test_nontemporal_store_nxv2i64(ptr %p, <vscale x 2 x i64> %v) {
70; CHECK-RV64V-LABEL: test_nontemporal_store_nxv2i64:
71; CHECK-RV64V:       # %bb.0:
72; CHECK-RV64V-NEXT:    ntl.all
73; CHECK-RV64V-NEXT:    vs2r.v v8, (a0)
74; CHECK-RV64V-NEXT:    ret
75;
76; CHECK-RV32V-LABEL: test_nontemporal_store_nxv2i64:
77; CHECK-RV32V:       # %bb.0:
78; CHECK-RV32V-NEXT:    ntl.all
79; CHECK-RV32V-NEXT:    vs2r.v v8, (a0)
80; CHECK-RV32V-NEXT:    ret
81  store <vscale x 2 x i64> %v, ptr %p, !nontemporal !0
82  ret void
83}
84
85define void @test_nontemporal_store_nxv4i32(ptr %p, <vscale x 4 x i32> %v) {
86; CHECK-RV64V-LABEL: test_nontemporal_store_nxv4i32:
87; CHECK-RV64V:       # %bb.0:
88; CHECK-RV64V-NEXT:    ntl.all
89; CHECK-RV64V-NEXT:    vs2r.v v8, (a0)
90; CHECK-RV64V-NEXT:    ret
91;
92; CHECK-RV32V-LABEL: test_nontemporal_store_nxv4i32:
93; CHECK-RV32V:       # %bb.0:
94; CHECK-RV32V-NEXT:    ntl.all
95; CHECK-RV32V-NEXT:    vs2r.v v8, (a0)
96; CHECK-RV32V-NEXT:    ret
97  store <vscale x 4 x i32> %v, ptr %p, !nontemporal !0
98  ret void
99}
100
101define void @test_nontemporal_store_nxv8i16(ptr %p, <vscale x 8 x i16> %v) {
102; CHECK-RV64V-LABEL: test_nontemporal_store_nxv8i16:
103; CHECK-RV64V:       # %bb.0:
104; CHECK-RV64V-NEXT:    ntl.all
105; CHECK-RV64V-NEXT:    vs2r.v v8, (a0)
106; CHECK-RV64V-NEXT:    ret
107;
108; CHECK-RV32V-LABEL: test_nontemporal_store_nxv8i16:
109; CHECK-RV32V:       # %bb.0:
110; CHECK-RV32V-NEXT:    ntl.all
111; CHECK-RV32V-NEXT:    vs2r.v v8, (a0)
112; CHECK-RV32V-NEXT:    ret
113  store <vscale x 8 x i16> %v, ptr %p, !nontemporal !0
114  ret void
115}
116
117define void @test_nontemporal_store_nxv16i8(ptr %p, <vscale x 16 x i8> %v) {
118; CHECK-RV64V-LABEL: test_nontemporal_store_nxv16i8:
119; CHECK-RV64V:       # %bb.0:
120; CHECK-RV64V-NEXT:    ntl.all
121; CHECK-RV64V-NEXT:    vs2r.v v8, (a0)
122; CHECK-RV64V-NEXT:    ret
123;
124; CHECK-RV32V-LABEL: test_nontemporal_store_nxv16i8:
125; CHECK-RV32V:       # %bb.0:
126; CHECK-RV32V-NEXT:    ntl.all
127; CHECK-RV32V-NEXT:    vs2r.v v8, (a0)
128; CHECK-RV32V-NEXT:    ret
129  store <vscale x 16 x i8> %v, ptr %p, !nontemporal !0
130  ret void
131}
132
133define <vscale x 2 x i64> @test_nontemporal_P1_load_nxv2i64(ptr %p) {
134; CHECK-RV64V-LABEL: test_nontemporal_P1_load_nxv2i64:
135; CHECK-RV64V:       # %bb.0:
136; CHECK-RV64V-NEXT:    ntl.p1
137; CHECK-RV64V-NEXT:    vl2re64.v v8, (a0)
138; CHECK-RV64V-NEXT:    ret
139;
140; CHECK-RV32V-LABEL: test_nontemporal_P1_load_nxv2i64:
141; CHECK-RV32V:       # %bb.0:
142; CHECK-RV32V-NEXT:    ntl.p1
143; CHECK-RV32V-NEXT:    vl2re64.v v8, (a0)
144; CHECK-RV32V-NEXT:    ret
145  %1 = load <vscale x 2 x i64>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
146  ret <vscale x 2 x i64> %1
147}
148
149define <vscale x 4 x i32> @test_nontemporal_P1_load_nxv4i32(ptr %p) {
150; CHECK-RV64V-LABEL: test_nontemporal_P1_load_nxv4i32:
151; CHECK-RV64V:       # %bb.0:
152; CHECK-RV64V-NEXT:    ntl.p1
153; CHECK-RV64V-NEXT:    vl2re32.v v8, (a0)
154; CHECK-RV64V-NEXT:    ret
155;
156; CHECK-RV32V-LABEL: test_nontemporal_P1_load_nxv4i32:
157; CHECK-RV32V:       # %bb.0:
158; CHECK-RV32V-NEXT:    ntl.p1
159; CHECK-RV32V-NEXT:    vl2re32.v v8, (a0)
160; CHECK-RV32V-NEXT:    ret
161  %1 = load <vscale x 4 x i32>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
162  ret <vscale x 4 x i32> %1
163}
164
165define <vscale x 8 x i16> @test_nontemporal_P1_load_nxv8i16(ptr %p) {
166; CHECK-RV64V-LABEL: test_nontemporal_P1_load_nxv8i16:
167; CHECK-RV64V:       # %bb.0:
168; CHECK-RV64V-NEXT:    ntl.p1
169; CHECK-RV64V-NEXT:    vl2re16.v v8, (a0)
170; CHECK-RV64V-NEXT:    ret
171;
172; CHECK-RV32V-LABEL: test_nontemporal_P1_load_nxv8i16:
173; CHECK-RV32V:       # %bb.0:
174; CHECK-RV32V-NEXT:    ntl.p1
175; CHECK-RV32V-NEXT:    vl2re16.v v8, (a0)
176; CHECK-RV32V-NEXT:    ret
177  %1 = load <vscale x 8 x i16>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
178  ret <vscale x 8 x i16> %1
179}
180
181define <vscale x 16 x i8> @test_nontemporal_P1_load_nxv16i8(ptr %p) {
182; CHECK-RV64V-LABEL: test_nontemporal_P1_load_nxv16i8:
183; CHECK-RV64V:       # %bb.0:
184; CHECK-RV64V-NEXT:    ntl.p1
185; CHECK-RV64V-NEXT:    vl2r.v v8, (a0)
186; CHECK-RV64V-NEXT:    ret
187;
188; CHECK-RV32V-LABEL: test_nontemporal_P1_load_nxv16i8:
189; CHECK-RV32V:       # %bb.0:
190; CHECK-RV32V-NEXT:    ntl.p1
191; CHECK-RV32V-NEXT:    vl2r.v v8, (a0)
192; CHECK-RV32V-NEXT:    ret
193  %1 = load <vscale x 16 x i8>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
194  ret <vscale x 16 x i8> %1
195}
196
197define void @test_nontemporal_P1_store_nxv2i64(ptr %p, <vscale x 2 x i64> %v) {
198; CHECK-RV64V-LABEL: test_nontemporal_P1_store_nxv2i64:
199; CHECK-RV64V:       # %bb.0:
200; CHECK-RV64V-NEXT:    ntl.p1
201; CHECK-RV64V-NEXT:    vs2r.v v8, (a0)
202; CHECK-RV64V-NEXT:    ret
203;
204; CHECK-RV32V-LABEL: test_nontemporal_P1_store_nxv2i64:
205; CHECK-RV32V:       # %bb.0:
206; CHECK-RV32V-NEXT:    ntl.p1
207; CHECK-RV32V-NEXT:    vs2r.v v8, (a0)
208; CHECK-RV32V-NEXT:    ret
209  store <vscale x 2 x i64> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
210  ret void
211}
212
213define void @test_nontemporal_P1_store_nxv4i32(ptr %p, <vscale x 4 x i32> %v) {
214; CHECK-RV64V-LABEL: test_nontemporal_P1_store_nxv4i32:
215; CHECK-RV64V:       # %bb.0:
216; CHECK-RV64V-NEXT:    ntl.p1
217; CHECK-RV64V-NEXT:    vs2r.v v8, (a0)
218; CHECK-RV64V-NEXT:    ret
219;
220; CHECK-RV32V-LABEL: test_nontemporal_P1_store_nxv4i32:
221; CHECK-RV32V:       # %bb.0:
222; CHECK-RV32V-NEXT:    ntl.p1
223; CHECK-RV32V-NEXT:    vs2r.v v8, (a0)
224; CHECK-RV32V-NEXT:    ret
225  store <vscale x 4 x i32> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
226  ret void
227}
228
229define void @test_nontemporal_P1_store_nxv8i16(ptr %p, <vscale x 8 x i16> %v) {
230; CHECK-RV64V-LABEL: test_nontemporal_P1_store_nxv8i16:
231; CHECK-RV64V:       # %bb.0:
232; CHECK-RV64V-NEXT:    ntl.p1
233; CHECK-RV64V-NEXT:    vs2r.v v8, (a0)
234; CHECK-RV64V-NEXT:    ret
235;
236; CHECK-RV32V-LABEL: test_nontemporal_P1_store_nxv8i16:
237; CHECK-RV32V:       # %bb.0:
238; CHECK-RV32V-NEXT:    ntl.p1
239; CHECK-RV32V-NEXT:    vs2r.v v8, (a0)
240; CHECK-RV32V-NEXT:    ret
241  store <vscale x 8 x i16> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
242  ret void
243}
244
245define void @test_nontemporal_P1_store_nxv16i8(ptr %p, <vscale x 16 x i8> %v) {
246; CHECK-RV64V-LABEL: test_nontemporal_P1_store_nxv16i8:
247; CHECK-RV64V:       # %bb.0:
248; CHECK-RV64V-NEXT:    ntl.p1
249; CHECK-RV64V-NEXT:    vs2r.v v8, (a0)
250; CHECK-RV64V-NEXT:    ret
251;
252; CHECK-RV32V-LABEL: test_nontemporal_P1_store_nxv16i8:
253; CHECK-RV32V:       # %bb.0:
254; CHECK-RV32V-NEXT:    ntl.p1
255; CHECK-RV32V-NEXT:    vs2r.v v8, (a0)
256; CHECK-RV32V-NEXT:    ret
257  store <vscale x 16 x i8> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
258  ret void
259}
260
261define <vscale x 2 x i64> @test_nontemporal_PALL_load_nxv2i64(ptr %p) {
262; CHECK-RV64V-LABEL: test_nontemporal_PALL_load_nxv2i64:
263; CHECK-RV64V:       # %bb.0:
264; CHECK-RV64V-NEXT:    ntl.pall
265; CHECK-RV64V-NEXT:    vl2re64.v v8, (a0)
266; CHECK-RV64V-NEXT:    ret
267;
268; CHECK-RV32V-LABEL: test_nontemporal_PALL_load_nxv2i64:
269; CHECK-RV32V:       # %bb.0:
270; CHECK-RV32V-NEXT:    ntl.pall
271; CHECK-RV32V-NEXT:    vl2re64.v v8, (a0)
272; CHECK-RV32V-NEXT:    ret
273  %1 = load <vscale x 2 x i64>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
274  ret <vscale x 2 x i64> %1
275}
276
277define <vscale x 4 x i32> @test_nontemporal_PALL_load_nxv4i32(ptr %p) {
278; CHECK-RV64V-LABEL: test_nontemporal_PALL_load_nxv4i32:
279; CHECK-RV64V:       # %bb.0:
280; CHECK-RV64V-NEXT:    ntl.pall
281; CHECK-RV64V-NEXT:    vl2re32.v v8, (a0)
282; CHECK-RV64V-NEXT:    ret
283;
284; CHECK-RV32V-LABEL: test_nontemporal_PALL_load_nxv4i32:
285; CHECK-RV32V:       # %bb.0:
286; CHECK-RV32V-NEXT:    ntl.pall
287; CHECK-RV32V-NEXT:    vl2re32.v v8, (a0)
288; CHECK-RV32V-NEXT:    ret
289  %1 = load <vscale x 4 x i32>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
290  ret <vscale x 4 x i32> %1
291}
292
293define <vscale x 8 x i16> @test_nontemporal_PALL_load_nxv8i16(ptr %p) {
294; CHECK-RV64V-LABEL: test_nontemporal_PALL_load_nxv8i16:
295; CHECK-RV64V:       # %bb.0:
296; CHECK-RV64V-NEXT:    ntl.pall
297; CHECK-RV64V-NEXT:    vl2re16.v v8, (a0)
298; CHECK-RV64V-NEXT:    ret
299;
300; CHECK-RV32V-LABEL: test_nontemporal_PALL_load_nxv8i16:
301; CHECK-RV32V:       # %bb.0:
302; CHECK-RV32V-NEXT:    ntl.pall
303; CHECK-RV32V-NEXT:    vl2re16.v v8, (a0)
304; CHECK-RV32V-NEXT:    ret
305  %1 = load <vscale x 8 x i16>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
306  ret <vscale x 8 x i16> %1
307}
308
309define <vscale x 16 x i8> @test_nontemporal_PALL_load_nxv16i8(ptr %p) {
310; CHECK-RV64V-LABEL: test_nontemporal_PALL_load_nxv16i8:
311; CHECK-RV64V:       # %bb.0:
312; CHECK-RV64V-NEXT:    ntl.pall
313; CHECK-RV64V-NEXT:    vl2r.v v8, (a0)
314; CHECK-RV64V-NEXT:    ret
315;
316; CHECK-RV32V-LABEL: test_nontemporal_PALL_load_nxv16i8:
317; CHECK-RV32V:       # %bb.0:
318; CHECK-RV32V-NEXT:    ntl.pall
319; CHECK-RV32V-NEXT:    vl2r.v v8, (a0)
320; CHECK-RV32V-NEXT:    ret
321  %1 = load <vscale x 16 x i8>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
322  ret <vscale x 16 x i8> %1
323}
324
325define void @test_nontemporal_PALL_store_nxv2i64(ptr %p, <vscale x 2 x i64> %v) {
326; CHECK-RV64V-LABEL: test_nontemporal_PALL_store_nxv2i64:
327; CHECK-RV64V:       # %bb.0:
328; CHECK-RV64V-NEXT:    ntl.pall
329; CHECK-RV64V-NEXT:    vs2r.v v8, (a0)
330; CHECK-RV64V-NEXT:    ret
331;
332; CHECK-RV32V-LABEL: test_nontemporal_PALL_store_nxv2i64:
333; CHECK-RV32V:       # %bb.0:
334; CHECK-RV32V-NEXT:    ntl.pall
335; CHECK-RV32V-NEXT:    vs2r.v v8, (a0)
336; CHECK-RV32V-NEXT:    ret
337  store <vscale x 2 x i64> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
338  ret void
339}
340
341define void @test_nontemporal_PALL_store_nxv4i32(ptr %p, <vscale x 4 x i32> %v) {
342; CHECK-RV64V-LABEL: test_nontemporal_PALL_store_nxv4i32:
343; CHECK-RV64V:       # %bb.0:
344; CHECK-RV64V-NEXT:    ntl.pall
345; CHECK-RV64V-NEXT:    vs2r.v v8, (a0)
346; CHECK-RV64V-NEXT:    ret
347;
348; CHECK-RV32V-LABEL: test_nontemporal_PALL_store_nxv4i32:
349; CHECK-RV32V:       # %bb.0:
350; CHECK-RV32V-NEXT:    ntl.pall
351; CHECK-RV32V-NEXT:    vs2r.v v8, (a0)
352; CHECK-RV32V-NEXT:    ret
353  store <vscale x 4 x i32> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
354  ret void
355}
356
357define void @test_nontemporal_PALL_store_nxv8i16(ptr %p, <vscale x 8 x i16> %v) {
358; CHECK-RV64V-LABEL: test_nontemporal_PALL_store_nxv8i16:
359; CHECK-RV64V:       # %bb.0:
360; CHECK-RV64V-NEXT:    ntl.pall
361; CHECK-RV64V-NEXT:    vs2r.v v8, (a0)
362; CHECK-RV64V-NEXT:    ret
363;
364; CHECK-RV32V-LABEL: test_nontemporal_PALL_store_nxv8i16:
365; CHECK-RV32V:       # %bb.0:
366; CHECK-RV32V-NEXT:    ntl.pall
367; CHECK-RV32V-NEXT:    vs2r.v v8, (a0)
368; CHECK-RV32V-NEXT:    ret
369  store <vscale x 8 x i16> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
370  ret void
371}
372
373define void @test_nontemporal_PALL_store_nxv16i8(ptr %p, <vscale x 16 x i8> %v) {
374; CHECK-RV64V-LABEL: test_nontemporal_PALL_store_nxv16i8:
375; CHECK-RV64V:       # %bb.0:
376; CHECK-RV64V-NEXT:    ntl.pall
377; CHECK-RV64V-NEXT:    vs2r.v v8, (a0)
378; CHECK-RV64V-NEXT:    ret
379;
380; CHECK-RV32V-LABEL: test_nontemporal_PALL_store_nxv16i8:
381; CHECK-RV32V:       # %bb.0:
382; CHECK-RV32V-NEXT:    ntl.pall
383; CHECK-RV32V-NEXT:    vs2r.v v8, (a0)
384; CHECK-RV32V-NEXT:    ret
385  store <vscale x 16 x i8> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
386  ret void
387}
388
389define <vscale x 2 x i64> @test_nontemporal_S1_load_nxv2i64(ptr %p) {
390; CHECK-RV64V-LABEL: test_nontemporal_S1_load_nxv2i64:
391; CHECK-RV64V:       # %bb.0:
392; CHECK-RV64V-NEXT:    ntl.s1
393; CHECK-RV64V-NEXT:    vl2re64.v v8, (a0)
394; CHECK-RV64V-NEXT:    ret
395;
396; CHECK-RV32V-LABEL: test_nontemporal_S1_load_nxv2i64:
397; CHECK-RV32V:       # %bb.0:
398; CHECK-RV32V-NEXT:    ntl.s1
399; CHECK-RV32V-NEXT:    vl2re64.v v8, (a0)
400; CHECK-RV32V-NEXT:    ret
401  %1 = load <vscale x 2 x i64>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
402  ret <vscale x 2 x i64> %1
403}
404
405define <vscale x 4 x i32> @test_nontemporal_S1_load_nxv4i32(ptr %p) {
406; CHECK-RV64V-LABEL: test_nontemporal_S1_load_nxv4i32:
407; CHECK-RV64V:       # %bb.0:
408; CHECK-RV64V-NEXT:    ntl.s1
409; CHECK-RV64V-NEXT:    vl2re32.v v8, (a0)
410; CHECK-RV64V-NEXT:    ret
411;
412; CHECK-RV32V-LABEL: test_nontemporal_S1_load_nxv4i32:
413; CHECK-RV32V:       # %bb.0:
414; CHECK-RV32V-NEXT:    ntl.s1
415; CHECK-RV32V-NEXT:    vl2re32.v v8, (a0)
416; CHECK-RV32V-NEXT:    ret
417  %1 = load <vscale x 4 x i32>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
418  ret <vscale x 4 x i32> %1
419}
420
421define <vscale x 8 x i16> @test_nontemporal_S1_load_nxv8i16(ptr %p) {
422; CHECK-RV64V-LABEL: test_nontemporal_S1_load_nxv8i16:
423; CHECK-RV64V:       # %bb.0:
424; CHECK-RV64V-NEXT:    ntl.s1
425; CHECK-RV64V-NEXT:    vl2re16.v v8, (a0)
426; CHECK-RV64V-NEXT:    ret
427;
428; CHECK-RV32V-LABEL: test_nontemporal_S1_load_nxv8i16:
429; CHECK-RV32V:       # %bb.0:
430; CHECK-RV32V-NEXT:    ntl.s1
431; CHECK-RV32V-NEXT:    vl2re16.v v8, (a0)
432; CHECK-RV32V-NEXT:    ret
433  %1 = load <vscale x 8 x i16>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
434  ret <vscale x 8 x i16> %1
435}
436
437define <vscale x 16 x i8> @test_nontemporal_S1_load_nxv16i8(ptr %p) {
438; CHECK-RV64V-LABEL: test_nontemporal_S1_load_nxv16i8:
439; CHECK-RV64V:       # %bb.0:
440; CHECK-RV64V-NEXT:    ntl.s1
441; CHECK-RV64V-NEXT:    vl2r.v v8, (a0)
442; CHECK-RV64V-NEXT:    ret
443;
444; CHECK-RV32V-LABEL: test_nontemporal_S1_load_nxv16i8:
445; CHECK-RV32V:       # %bb.0:
446; CHECK-RV32V-NEXT:    ntl.s1
447; CHECK-RV32V-NEXT:    vl2r.v v8, (a0)
448; CHECK-RV32V-NEXT:    ret
449  %1 = load <vscale x 16 x i8>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
450  ret <vscale x 16 x i8> %1
451}
452
453define void @test_nontemporal_S1_store_nxv2i64(ptr %p, <vscale x 2 x i64> %v) {
454; CHECK-RV64V-LABEL: test_nontemporal_S1_store_nxv2i64:
455; CHECK-RV64V:       # %bb.0:
456; CHECK-RV64V-NEXT:    ntl.s1
457; CHECK-RV64V-NEXT:    vs2r.v v8, (a0)
458; CHECK-RV64V-NEXT:    ret
459;
460; CHECK-RV32V-LABEL: test_nontemporal_S1_store_nxv2i64:
461; CHECK-RV32V:       # %bb.0:
462; CHECK-RV32V-NEXT:    ntl.s1
463; CHECK-RV32V-NEXT:    vs2r.v v8, (a0)
464; CHECK-RV32V-NEXT:    ret
465  store <vscale x 2 x i64> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
466  ret void
467}
468
469define void @test_nontemporal_S1_store_nxv4i32(ptr %p, <vscale x 4 x i32> %v) {
470; CHECK-RV64V-LABEL: test_nontemporal_S1_store_nxv4i32:
471; CHECK-RV64V:       # %bb.0:
472; CHECK-RV64V-NEXT:    ntl.s1
473; CHECK-RV64V-NEXT:    vs2r.v v8, (a0)
474; CHECK-RV64V-NEXT:    ret
475;
476; CHECK-RV32V-LABEL: test_nontemporal_S1_store_nxv4i32:
477; CHECK-RV32V:       # %bb.0:
478; CHECK-RV32V-NEXT:    ntl.s1
479; CHECK-RV32V-NEXT:    vs2r.v v8, (a0)
480; CHECK-RV32V-NEXT:    ret
481  store <vscale x 4 x i32> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
482  ret void
483}
484
485define void @test_nontemporal_S1_store_nxv8i16(ptr %p, <vscale x 8 x i16> %v) {
486; CHECK-RV64V-LABEL: test_nontemporal_S1_store_nxv8i16:
487; CHECK-RV64V:       # %bb.0:
488; CHECK-RV64V-NEXT:    ntl.s1
489; CHECK-RV64V-NEXT:    vs2r.v v8, (a0)
490; CHECK-RV64V-NEXT:    ret
491;
492; CHECK-RV32V-LABEL: test_nontemporal_S1_store_nxv8i16:
493; CHECK-RV32V:       # %bb.0:
494; CHECK-RV32V-NEXT:    ntl.s1
495; CHECK-RV32V-NEXT:    vs2r.v v8, (a0)
496; CHECK-RV32V-NEXT:    ret
497  store <vscale x 8 x i16> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
498  ret void
499}
500
501define void @test_nontemporal_S1_store_nxv16i8(ptr %p, <vscale x 16 x i8> %v) {
502; CHECK-RV64V-LABEL: test_nontemporal_S1_store_nxv16i8:
503; CHECK-RV64V:       # %bb.0:
504; CHECK-RV64V-NEXT:    ntl.s1
505; CHECK-RV64V-NEXT:    vs2r.v v8, (a0)
506; CHECK-RV64V-NEXT:    ret
507;
508; CHECK-RV32V-LABEL: test_nontemporal_S1_store_nxv16i8:
509; CHECK-RV32V:       # %bb.0:
510; CHECK-RV32V-NEXT:    ntl.s1
511; CHECK-RV32V-NEXT:    vs2r.v v8, (a0)
512; CHECK-RV32V-NEXT:    ret
513  store <vscale x 16 x i8> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
514  ret void
515}
516
517define <vscale x 2 x i64> @test_nontemporal_ALL_load_nxv2i64(ptr %p) {
518; CHECK-RV64V-LABEL: test_nontemporal_ALL_load_nxv2i64:
519; CHECK-RV64V:       # %bb.0:
520; CHECK-RV64V-NEXT:    ntl.all
521; CHECK-RV64V-NEXT:    vl2re64.v v8, (a0)
522; CHECK-RV64V-NEXT:    ret
523;
524; CHECK-RV32V-LABEL: test_nontemporal_ALL_load_nxv2i64:
525; CHECK-RV32V:       # %bb.0:
526; CHECK-RV32V-NEXT:    ntl.all
527; CHECK-RV32V-NEXT:    vl2re64.v v8, (a0)
528; CHECK-RV32V-NEXT:    ret
529  %1 = load <vscale x 2 x i64>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
530  ret <vscale x 2 x i64> %1
531}
532
533define <vscale x 4 x i32> @test_nontemporal_ALL_load_nxv4i32(ptr %p) {
534; CHECK-RV64V-LABEL: test_nontemporal_ALL_load_nxv4i32:
535; CHECK-RV64V:       # %bb.0:
536; CHECK-RV64V-NEXT:    ntl.all
537; CHECK-RV64V-NEXT:    vl2re32.v v8, (a0)
538; CHECK-RV64V-NEXT:    ret
539;
540; CHECK-RV32V-LABEL: test_nontemporal_ALL_load_nxv4i32:
541; CHECK-RV32V:       # %bb.0:
542; CHECK-RV32V-NEXT:    ntl.all
543; CHECK-RV32V-NEXT:    vl2re32.v v8, (a0)
544; CHECK-RV32V-NEXT:    ret
545  %1 = load <vscale x 4 x i32>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
546  ret <vscale x 4 x i32> %1
547}
548
549define <vscale x 8 x i16> @test_nontemporal_ALL_load_nxv8i16(ptr %p) {
550; CHECK-RV64V-LABEL: test_nontemporal_ALL_load_nxv8i16:
551; CHECK-RV64V:       # %bb.0:
552; CHECK-RV64V-NEXT:    ntl.all
553; CHECK-RV64V-NEXT:    vl2re16.v v8, (a0)
554; CHECK-RV64V-NEXT:    ret
555;
556; CHECK-RV32V-LABEL: test_nontemporal_ALL_load_nxv8i16:
557; CHECK-RV32V:       # %bb.0:
558; CHECK-RV32V-NEXT:    ntl.all
559; CHECK-RV32V-NEXT:    vl2re16.v v8, (a0)
560; CHECK-RV32V-NEXT:    ret
561  %1 = load <vscale x 8 x i16>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
562  ret <vscale x 8 x i16> %1
563}
564
565define <vscale x 16 x i8> @test_nontemporal_ALL_load_nxv16i8(ptr %p) {
566; CHECK-RV64V-LABEL: test_nontemporal_ALL_load_nxv16i8:
567; CHECK-RV64V:       # %bb.0:
568; CHECK-RV64V-NEXT:    ntl.all
569; CHECK-RV64V-NEXT:    vl2r.v v8, (a0)
570; CHECK-RV64V-NEXT:    ret
571;
572; CHECK-RV32V-LABEL: test_nontemporal_ALL_load_nxv16i8:
573; CHECK-RV32V:       # %bb.0:
574; CHECK-RV32V-NEXT:    ntl.all
575; CHECK-RV32V-NEXT:    vl2r.v v8, (a0)
576; CHECK-RV32V-NEXT:    ret
577  %1 = load <vscale x 16 x i8>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
578  ret <vscale x 16 x i8> %1
579}
580
581define void @test_nontemporal_ALL_store_nxv2i64(ptr %p, <vscale x 2 x i64> %v) {
582; CHECK-RV64V-LABEL: test_nontemporal_ALL_store_nxv2i64:
583; CHECK-RV64V:       # %bb.0:
584; CHECK-RV64V-NEXT:    ntl.all
585; CHECK-RV64V-NEXT:    vs2r.v v8, (a0)
586; CHECK-RV64V-NEXT:    ret
587;
588; CHECK-RV32V-LABEL: test_nontemporal_ALL_store_nxv2i64:
589; CHECK-RV32V:       # %bb.0:
590; CHECK-RV32V-NEXT:    ntl.all
591; CHECK-RV32V-NEXT:    vs2r.v v8, (a0)
592; CHECK-RV32V-NEXT:    ret
593  store <vscale x 2 x i64> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
594  ret void
595}
596
597define void @test_nontemporal_ALL_store_nxv4i32(ptr %p, <vscale x 4 x i32> %v) {
598; CHECK-RV64V-LABEL: test_nontemporal_ALL_store_nxv4i32:
599; CHECK-RV64V:       # %bb.0:
600; CHECK-RV64V-NEXT:    ntl.all
601; CHECK-RV64V-NEXT:    vs2r.v v8, (a0)
602; CHECK-RV64V-NEXT:    ret
603;
604; CHECK-RV32V-LABEL: test_nontemporal_ALL_store_nxv4i32:
605; CHECK-RV32V:       # %bb.0:
606; CHECK-RV32V-NEXT:    ntl.all
607; CHECK-RV32V-NEXT:    vs2r.v v8, (a0)
608; CHECK-RV32V-NEXT:    ret
609  store <vscale x 4 x i32> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
610  ret void
611}
612
613define void @test_nontemporal_ALL_store_nxv8i16(ptr %p, <vscale x 8 x i16> %v) {
614; CHECK-RV64V-LABEL: test_nontemporal_ALL_store_nxv8i16:
615; CHECK-RV64V:       # %bb.0:
616; CHECK-RV64V-NEXT:    ntl.all
617; CHECK-RV64V-NEXT:    vs2r.v v8, (a0)
618; CHECK-RV64V-NEXT:    ret
619;
620; CHECK-RV32V-LABEL: test_nontemporal_ALL_store_nxv8i16:
621; CHECK-RV32V:       # %bb.0:
622; CHECK-RV32V-NEXT:    ntl.all
623; CHECK-RV32V-NEXT:    vs2r.v v8, (a0)
624; CHECK-RV32V-NEXT:    ret
625  store <vscale x 8 x i16> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
626  ret void
627}
628
629define void @test_nontemporal_ALL_store_nxv16i8(ptr %p, <vscale x 16 x i8> %v) {
630; CHECK-RV64V-LABEL: test_nontemporal_ALL_store_nxv16i8:
631; CHECK-RV64V:       # %bb.0:
632; CHECK-RV64V-NEXT:    ntl.all
633; CHECK-RV64V-NEXT:    vs2r.v v8, (a0)
634; CHECK-RV64V-NEXT:    ret
635;
636; CHECK-RV32V-LABEL: test_nontemporal_ALL_store_nxv16i8:
637; CHECK-RV32V:       # %bb.0:
638; CHECK-RV32V-NEXT:    ntl.all
639; CHECK-RV32V-NEXT:    vs2r.v v8, (a0)
640; CHECK-RV32V-NEXT:    ret
641  store <vscale x 16 x i8> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
642  ret void
643}
644
645!0 = !{i32 1}
646!1 = !{i32 2}
647!2 = !{i32 3}
648!3 = !{i32 4}
649!4 = !{i32 5}
650