xref: /llvm-project/llvm/test/CodeGen/RISCV/misched-load-clustering.ll (revision 2967e5f8007d873a3e9d97870d2461d0827a3976)
1; REQUIRES: asserts
2; RUN: llc -mtriple=riscv32 -verify-misched -riscv-misched-load-store-clustering=false \
3; RUN:     -debug-only=machine-scheduler -o - 2>&1 < %s \
4; RUN:   | FileCheck -check-prefix=NOCLUSTER %s
5; RUN: llc -mtriple=riscv64 -verify-misched -riscv-misched-load-store-clustering=false \
6; RUN:     -debug-only=machine-scheduler -o - 2>&1 < %s \
7; RUN:   | FileCheck -check-prefix=NOCLUSTER %s
8; RUN: llc -mtriple=riscv32 -verify-misched \
9; RUN:     -debug-only=machine-scheduler -o - 2>&1 < %s \
10; RUN:   | FileCheck -check-prefix=LDCLUSTER %s
11; RUN: llc -mtriple=riscv64 -verify-misched \
12; RUN:     -debug-only=machine-scheduler -o - 2>&1 < %s \
13; RUN:   | FileCheck -check-prefix=LDCLUSTER %s
14
15
16define i32 @load_clustering_1(ptr nocapture %p) {
17; NOCLUSTER: ********** MI Scheduling **********
18; NOCLUSTER-LABEL: load_clustering_1:%bb.0
19; NOCLUSTER: *** Final schedule for %bb.0 ***
20; NOCLUSTER: SU(1): %1:gpr = LW %0:gpr, 12
21; NOCLUSTER: SU(2): %2:gpr = LW %0:gpr, 8
22; NOCLUSTER: SU(4): %4:gpr = LW %0:gpr, 4
23; NOCLUSTER: SU(5): %6:gpr = LW %0:gpr, 16
24;
25; LDCLUSTER: ********** MI Scheduling **********
26; LDCLUSTER-LABEL: load_clustering_1:%bb.0
27; LDCLUSTER: *** Final schedule for %bb.0 ***
28; LDCLUSTER: SU(4): %4:gpr = LW %0:gpr, 4
29; LDCLUSTER: SU(2): %2:gpr = LW %0:gpr, 8
30; LDCLUSTER: SU(1): %1:gpr = LW %0:gpr, 12
31; LDCLUSTER: SU(5): %6:gpr = LW %0:gpr, 16
32entry:
33  %arrayidx0 = getelementptr inbounds i32, ptr %p, i32 3
34  %val0 = load i32, ptr %arrayidx0
35  %arrayidx1 = getelementptr inbounds i32, ptr %p, i32 2
36  %val1 = load i32, ptr %arrayidx1
37  %tmp0 = add i32 %val0, %val1
38  %arrayidx2 = getelementptr inbounds i32, ptr %p, i32 1
39  %val2 = load i32, ptr %arrayidx2
40  %tmp1 = add i32 %tmp0, %val2
41  %arrayidx3 = getelementptr inbounds i32, ptr %p, i32 4
42  %val3 = load i32, ptr %arrayidx3
43  %tmp2 = add i32 %tmp1, %val3
44  ret i32 %tmp2
45}
46