xref: /llvm-project/llvm/test/CodeGen/RISCV/min-max.ll (revision 7b3bbd83c0c24087072ec5b22a76799ab31f87d5) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=riscv32 | FileCheck %s --check-prefixes=NOZBB,RV32I
3; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefixes=NOZBB,RV64I
4; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb | \
5; RUN:   FileCheck %s --check-prefixes=ZBB,RV32ZBB
6; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb | \
7; RUN:   FileCheck %s --check-prefixes=ZBB,RV64ZBB
8
9; Basic tests.
10
11declare i8 @llvm.smax.i8(i8 %a, i8 %b) readnone
12
13define signext i8 @smax_i8(i8 signext %a, i8 signext %b) {
14; NOZBB-LABEL: smax_i8:
15; NOZBB:       # %bb.0:
16; NOZBB-NEXT:    blt a1, a0, .LBB0_2
17; NOZBB-NEXT:  # %bb.1:
18; NOZBB-NEXT:    mv a0, a1
19; NOZBB-NEXT:  .LBB0_2:
20; NOZBB-NEXT:    ret
21;
22; ZBB-LABEL: smax_i8:
23; ZBB:       # %bb.0:
24; ZBB-NEXT:    max a0, a0, a1
25; ZBB-NEXT:    ret
26  %c = call i8 @llvm.smax.i8(i8 %a, i8 %b)
27  ret i8 %c
28}
29
30declare i16 @llvm.smax.i16(i16 %a, i16 %b) readnone
31
32define signext i16 @smax_i16(i16 signext %a, i16 signext %b) {
33; NOZBB-LABEL: smax_i16:
34; NOZBB:       # %bb.0:
35; NOZBB-NEXT:    blt a1, a0, .LBB1_2
36; NOZBB-NEXT:  # %bb.1:
37; NOZBB-NEXT:    mv a0, a1
38; NOZBB-NEXT:  .LBB1_2:
39; NOZBB-NEXT:    ret
40;
41; ZBB-LABEL: smax_i16:
42; ZBB:       # %bb.0:
43; ZBB-NEXT:    max a0, a0, a1
44; ZBB-NEXT:    ret
45  %c = call i16 @llvm.smax.i16(i16 %a, i16 %b)
46  ret i16 %c
47}
48
49declare i32 @llvm.smax.i32(i32 %a, i32 %b) readnone
50
51define signext i32 @smax_i32(i32 signext %a, i32 signext %b) {
52; NOZBB-LABEL: smax_i32:
53; NOZBB:       # %bb.0:
54; NOZBB-NEXT:    blt a1, a0, .LBB2_2
55; NOZBB-NEXT:  # %bb.1:
56; NOZBB-NEXT:    mv a0, a1
57; NOZBB-NEXT:  .LBB2_2:
58; NOZBB-NEXT:    ret
59;
60; ZBB-LABEL: smax_i32:
61; ZBB:       # %bb.0:
62; ZBB-NEXT:    max a0, a0, a1
63; ZBB-NEXT:    ret
64  %c = call i32 @llvm.smax.i32(i32 %a, i32 %b)
65  ret i32 %c
66}
67
68declare i64 @llvm.smax.i64(i64 %a, i64 %b) readnone
69
70define i64 @smax_i64(i64 %a, i64 %b) {
71; RV32I-LABEL: smax_i64:
72; RV32I:       # %bb.0:
73; RV32I-NEXT:    beq a1, a3, .LBB3_2
74; RV32I-NEXT:  # %bb.1:
75; RV32I-NEXT:    slt a4, a3, a1
76; RV32I-NEXT:    beqz a4, .LBB3_3
77; RV32I-NEXT:    j .LBB3_4
78; RV32I-NEXT:  .LBB3_2:
79; RV32I-NEXT:    sltu a4, a2, a0
80; RV32I-NEXT:    bnez a4, .LBB3_4
81; RV32I-NEXT:  .LBB3_3:
82; RV32I-NEXT:    mv a0, a2
83; RV32I-NEXT:    mv a1, a3
84; RV32I-NEXT:  .LBB3_4:
85; RV32I-NEXT:    ret
86;
87; RV64I-LABEL: smax_i64:
88; RV64I:       # %bb.0:
89; RV64I-NEXT:    blt a1, a0, .LBB3_2
90; RV64I-NEXT:  # %bb.1:
91; RV64I-NEXT:    mv a0, a1
92; RV64I-NEXT:  .LBB3_2:
93; RV64I-NEXT:    ret
94;
95; RV32ZBB-LABEL: smax_i64:
96; RV32ZBB:       # %bb.0:
97; RV32ZBB-NEXT:    beq a1, a3, .LBB3_2
98; RV32ZBB-NEXT:  # %bb.1:
99; RV32ZBB-NEXT:    slt a4, a3, a1
100; RV32ZBB-NEXT:    beqz a4, .LBB3_3
101; RV32ZBB-NEXT:    j .LBB3_4
102; RV32ZBB-NEXT:  .LBB3_2:
103; RV32ZBB-NEXT:    sltu a4, a2, a0
104; RV32ZBB-NEXT:    bnez a4, .LBB3_4
105; RV32ZBB-NEXT:  .LBB3_3:
106; RV32ZBB-NEXT:    mv a0, a2
107; RV32ZBB-NEXT:    mv a1, a3
108; RV32ZBB-NEXT:  .LBB3_4:
109; RV32ZBB-NEXT:    ret
110;
111; RV64ZBB-LABEL: smax_i64:
112; RV64ZBB:       # %bb.0:
113; RV64ZBB-NEXT:    max a0, a0, a1
114; RV64ZBB-NEXT:    ret
115  %c = call i64 @llvm.smax.i64(i64 %a, i64 %b)
116  ret i64 %c
117}
118
119declare i8 @llvm.smin.i8(i8 %a, i8 %b) readnone
120
121define signext i8 @smin_i8(i8 signext %a, i8 signext %b) {
122; NOZBB-LABEL: smin_i8:
123; NOZBB:       # %bb.0:
124; NOZBB-NEXT:    blt a0, a1, .LBB4_2
125; NOZBB-NEXT:  # %bb.1:
126; NOZBB-NEXT:    mv a0, a1
127; NOZBB-NEXT:  .LBB4_2:
128; NOZBB-NEXT:    ret
129;
130; ZBB-LABEL: smin_i8:
131; ZBB:       # %bb.0:
132; ZBB-NEXT:    min a0, a0, a1
133; ZBB-NEXT:    ret
134  %c = call i8 @llvm.smin.i8(i8 %a, i8 %b)
135  ret i8 %c
136}
137
138declare i16 @llvm.smin.i16(i16 %a, i16 %b) readnone
139
140define signext i16 @smin_i16(i16 signext %a, i16 signext %b) {
141; NOZBB-LABEL: smin_i16:
142; NOZBB:       # %bb.0:
143; NOZBB-NEXT:    blt a0, a1, .LBB5_2
144; NOZBB-NEXT:  # %bb.1:
145; NOZBB-NEXT:    mv a0, a1
146; NOZBB-NEXT:  .LBB5_2:
147; NOZBB-NEXT:    ret
148;
149; ZBB-LABEL: smin_i16:
150; ZBB:       # %bb.0:
151; ZBB-NEXT:    min a0, a0, a1
152; ZBB-NEXT:    ret
153  %c = call i16 @llvm.smin.i16(i16 %a, i16 %b)
154  ret i16 %c
155}
156
157declare i32 @llvm.smin.i32(i32 %a, i32 %b) readnone
158
159define signext i32 @smin_i32(i32 signext %a, i32 signext %b) {
160; NOZBB-LABEL: smin_i32:
161; NOZBB:       # %bb.0:
162; NOZBB-NEXT:    blt a0, a1, .LBB6_2
163; NOZBB-NEXT:  # %bb.1:
164; NOZBB-NEXT:    mv a0, a1
165; NOZBB-NEXT:  .LBB6_2:
166; NOZBB-NEXT:    ret
167;
168; ZBB-LABEL: smin_i32:
169; ZBB:       # %bb.0:
170; ZBB-NEXT:    min a0, a0, a1
171; ZBB-NEXT:    ret
172  %c = call i32 @llvm.smin.i32(i32 %a, i32 %b)
173  ret i32 %c
174}
175
176declare i64 @llvm.smin.i64(i64 %a, i64 %b) readnone
177
178define i64 @smin_i64(i64 %a, i64 %b) {
179; RV32I-LABEL: smin_i64:
180; RV32I:       # %bb.0:
181; RV32I-NEXT:    beq a1, a3, .LBB7_2
182; RV32I-NEXT:  # %bb.1:
183; RV32I-NEXT:    slt a4, a1, a3
184; RV32I-NEXT:    beqz a4, .LBB7_3
185; RV32I-NEXT:    j .LBB7_4
186; RV32I-NEXT:  .LBB7_2:
187; RV32I-NEXT:    sltu a4, a0, a2
188; RV32I-NEXT:    bnez a4, .LBB7_4
189; RV32I-NEXT:  .LBB7_3:
190; RV32I-NEXT:    mv a0, a2
191; RV32I-NEXT:    mv a1, a3
192; RV32I-NEXT:  .LBB7_4:
193; RV32I-NEXT:    ret
194;
195; RV64I-LABEL: smin_i64:
196; RV64I:       # %bb.0:
197; RV64I-NEXT:    blt a0, a1, .LBB7_2
198; RV64I-NEXT:  # %bb.1:
199; RV64I-NEXT:    mv a0, a1
200; RV64I-NEXT:  .LBB7_2:
201; RV64I-NEXT:    ret
202;
203; RV32ZBB-LABEL: smin_i64:
204; RV32ZBB:       # %bb.0:
205; RV32ZBB-NEXT:    beq a1, a3, .LBB7_2
206; RV32ZBB-NEXT:  # %bb.1:
207; RV32ZBB-NEXT:    slt a4, a1, a3
208; RV32ZBB-NEXT:    beqz a4, .LBB7_3
209; RV32ZBB-NEXT:    j .LBB7_4
210; RV32ZBB-NEXT:  .LBB7_2:
211; RV32ZBB-NEXT:    sltu a4, a0, a2
212; RV32ZBB-NEXT:    bnez a4, .LBB7_4
213; RV32ZBB-NEXT:  .LBB7_3:
214; RV32ZBB-NEXT:    mv a0, a2
215; RV32ZBB-NEXT:    mv a1, a3
216; RV32ZBB-NEXT:  .LBB7_4:
217; RV32ZBB-NEXT:    ret
218;
219; RV64ZBB-LABEL: smin_i64:
220; RV64ZBB:       # %bb.0:
221; RV64ZBB-NEXT:    min a0, a0, a1
222; RV64ZBB-NEXT:    ret
223  %c = call i64 @llvm.smin.i64(i64 %a, i64 %b)
224  ret i64 %c
225}
226
227declare i8 @llvm.umax.i8(i8 %a, i8 %b) readnone
228
229define i8 @umax_i8(i8 zeroext %a, i8 zeroext %b) {
230; NOZBB-LABEL: umax_i8:
231; NOZBB:       # %bb.0:
232; NOZBB-NEXT:    bltu a1, a0, .LBB8_2
233; NOZBB-NEXT:  # %bb.1:
234; NOZBB-NEXT:    mv a0, a1
235; NOZBB-NEXT:  .LBB8_2:
236; NOZBB-NEXT:    ret
237;
238; ZBB-LABEL: umax_i8:
239; ZBB:       # %bb.0:
240; ZBB-NEXT:    maxu a0, a0, a1
241; ZBB-NEXT:    ret
242  %c = call i8 @llvm.umax.i8(i8 %a, i8 %b)
243  ret i8 %c
244}
245
246declare i16 @llvm.umax.i16(i16 %a, i16 %b) readnone
247
248define i16 @umax_i16(i16 zeroext %a, i16 zeroext %b) {
249; NOZBB-LABEL: umax_i16:
250; NOZBB:       # %bb.0:
251; NOZBB-NEXT:    bltu a1, a0, .LBB9_2
252; NOZBB-NEXT:  # %bb.1:
253; NOZBB-NEXT:    mv a0, a1
254; NOZBB-NEXT:  .LBB9_2:
255; NOZBB-NEXT:    ret
256;
257; ZBB-LABEL: umax_i16:
258; ZBB:       # %bb.0:
259; ZBB-NEXT:    maxu a0, a0, a1
260; ZBB-NEXT:    ret
261  %c = call i16 @llvm.umax.i16(i16 %a, i16 %b)
262  ret i16 %c
263}
264
265declare i32 @llvm.umax.i32(i32 %a, i32 %b) readnone
266
267define signext i32 @umax_i32(i32 signext %a, i32 signext %b) {
268; NOZBB-LABEL: umax_i32:
269; NOZBB:       # %bb.0:
270; NOZBB-NEXT:    bltu a1, a0, .LBB10_2
271; NOZBB-NEXT:  # %bb.1:
272; NOZBB-NEXT:    mv a0, a1
273; NOZBB-NEXT:  .LBB10_2:
274; NOZBB-NEXT:    ret
275;
276; ZBB-LABEL: umax_i32:
277; ZBB:       # %bb.0:
278; ZBB-NEXT:    maxu a0, a0, a1
279; ZBB-NEXT:    ret
280  %c = call i32 @llvm.umax.i32(i32 %a, i32 %b)
281  ret i32 %c
282}
283
284declare i64 @llvm.umax.i64(i64 %a, i64 %b) readnone
285
286define i64 @umax_i64(i64 %a, i64 %b) {
287; RV32I-LABEL: umax_i64:
288; RV32I:       # %bb.0:
289; RV32I-NEXT:    beq a1, a3, .LBB11_2
290; RV32I-NEXT:  # %bb.1:
291; RV32I-NEXT:    sltu a4, a3, a1
292; RV32I-NEXT:    beqz a4, .LBB11_3
293; RV32I-NEXT:    j .LBB11_4
294; RV32I-NEXT:  .LBB11_2:
295; RV32I-NEXT:    sltu a4, a2, a0
296; RV32I-NEXT:    bnez a4, .LBB11_4
297; RV32I-NEXT:  .LBB11_3:
298; RV32I-NEXT:    mv a0, a2
299; RV32I-NEXT:    mv a1, a3
300; RV32I-NEXT:  .LBB11_4:
301; RV32I-NEXT:    ret
302;
303; RV64I-LABEL: umax_i64:
304; RV64I:       # %bb.0:
305; RV64I-NEXT:    bltu a1, a0, .LBB11_2
306; RV64I-NEXT:  # %bb.1:
307; RV64I-NEXT:    mv a0, a1
308; RV64I-NEXT:  .LBB11_2:
309; RV64I-NEXT:    ret
310;
311; RV32ZBB-LABEL: umax_i64:
312; RV32ZBB:       # %bb.0:
313; RV32ZBB-NEXT:    beq a1, a3, .LBB11_2
314; RV32ZBB-NEXT:  # %bb.1:
315; RV32ZBB-NEXT:    sltu a4, a3, a1
316; RV32ZBB-NEXT:    beqz a4, .LBB11_3
317; RV32ZBB-NEXT:    j .LBB11_4
318; RV32ZBB-NEXT:  .LBB11_2:
319; RV32ZBB-NEXT:    sltu a4, a2, a0
320; RV32ZBB-NEXT:    bnez a4, .LBB11_4
321; RV32ZBB-NEXT:  .LBB11_3:
322; RV32ZBB-NEXT:    mv a0, a2
323; RV32ZBB-NEXT:    mv a1, a3
324; RV32ZBB-NEXT:  .LBB11_4:
325; RV32ZBB-NEXT:    ret
326;
327; RV64ZBB-LABEL: umax_i64:
328; RV64ZBB:       # %bb.0:
329; RV64ZBB-NEXT:    maxu a0, a0, a1
330; RV64ZBB-NEXT:    ret
331  %c = call i64 @llvm.umax.i64(i64 %a, i64 %b)
332  ret i64 %c
333}
334
335declare i8 @llvm.umin.i8(i8 %a, i8 %b) readnone
336
337define zeroext i8 @umin_i8(i8 zeroext %a, i8 zeroext %b) {
338; NOZBB-LABEL: umin_i8:
339; NOZBB:       # %bb.0:
340; NOZBB-NEXT:    bltu a0, a1, .LBB12_2
341; NOZBB-NEXT:  # %bb.1:
342; NOZBB-NEXT:    mv a0, a1
343; NOZBB-NEXT:  .LBB12_2:
344; NOZBB-NEXT:    ret
345;
346; ZBB-LABEL: umin_i8:
347; ZBB:       # %bb.0:
348; ZBB-NEXT:    minu a0, a0, a1
349; ZBB-NEXT:    ret
350  %c = call i8 @llvm.umin.i8(i8 %a, i8 %b)
351  ret i8 %c
352}
353
354declare i16 @llvm.umin.i16(i16 %a, i16 %b) readnone
355
356define zeroext i16 @umin_i16(i16 zeroext %a, i16 zeroext %b) {
357; NOZBB-LABEL: umin_i16:
358; NOZBB:       # %bb.0:
359; NOZBB-NEXT:    bltu a0, a1, .LBB13_2
360; NOZBB-NEXT:  # %bb.1:
361; NOZBB-NEXT:    mv a0, a1
362; NOZBB-NEXT:  .LBB13_2:
363; NOZBB-NEXT:    ret
364;
365; ZBB-LABEL: umin_i16:
366; ZBB:       # %bb.0:
367; ZBB-NEXT:    minu a0, a0, a1
368; ZBB-NEXT:    ret
369  %c = call i16 @llvm.umin.i16(i16 %a, i16 %b)
370  ret i16 %c
371}
372
373declare i32 @llvm.umin.i32(i32 %a, i32 %b) readnone
374
375define signext i32 @umin_i32(i32 signext %a, i32 signext %b) {
376; NOZBB-LABEL: umin_i32:
377; NOZBB:       # %bb.0:
378; NOZBB-NEXT:    bltu a0, a1, .LBB14_2
379; NOZBB-NEXT:  # %bb.1:
380; NOZBB-NEXT:    mv a0, a1
381; NOZBB-NEXT:  .LBB14_2:
382; NOZBB-NEXT:    ret
383;
384; ZBB-LABEL: umin_i32:
385; ZBB:       # %bb.0:
386; ZBB-NEXT:    minu a0, a0, a1
387; ZBB-NEXT:    ret
388  %c = call i32 @llvm.umin.i32(i32 %a, i32 %b)
389  ret i32 %c
390}
391
392declare i64 @llvm.umin.i64(i64 %a, i64 %b) readnone
393
394define i64 @umin_i64(i64 %a, i64 %b) {
395; RV32I-LABEL: umin_i64:
396; RV32I:       # %bb.0:
397; RV32I-NEXT:    beq a1, a3, .LBB15_2
398; RV32I-NEXT:  # %bb.1:
399; RV32I-NEXT:    sltu a4, a1, a3
400; RV32I-NEXT:    beqz a4, .LBB15_3
401; RV32I-NEXT:    j .LBB15_4
402; RV32I-NEXT:  .LBB15_2:
403; RV32I-NEXT:    sltu a4, a0, a2
404; RV32I-NEXT:    bnez a4, .LBB15_4
405; RV32I-NEXT:  .LBB15_3:
406; RV32I-NEXT:    mv a0, a2
407; RV32I-NEXT:    mv a1, a3
408; RV32I-NEXT:  .LBB15_4:
409; RV32I-NEXT:    ret
410;
411; RV64I-LABEL: umin_i64:
412; RV64I:       # %bb.0:
413; RV64I-NEXT:    bltu a0, a1, .LBB15_2
414; RV64I-NEXT:  # %bb.1:
415; RV64I-NEXT:    mv a0, a1
416; RV64I-NEXT:  .LBB15_2:
417; RV64I-NEXT:    ret
418;
419; RV32ZBB-LABEL: umin_i64:
420; RV32ZBB:       # %bb.0:
421; RV32ZBB-NEXT:    beq a1, a3, .LBB15_2
422; RV32ZBB-NEXT:  # %bb.1:
423; RV32ZBB-NEXT:    sltu a4, a1, a3
424; RV32ZBB-NEXT:    beqz a4, .LBB15_3
425; RV32ZBB-NEXT:    j .LBB15_4
426; RV32ZBB-NEXT:  .LBB15_2:
427; RV32ZBB-NEXT:    sltu a4, a0, a2
428; RV32ZBB-NEXT:    bnez a4, .LBB15_4
429; RV32ZBB-NEXT:  .LBB15_3:
430; RV32ZBB-NEXT:    mv a0, a2
431; RV32ZBB-NEXT:    mv a1, a3
432; RV32ZBB-NEXT:  .LBB15_4:
433; RV32ZBB-NEXT:    ret
434;
435; RV64ZBB-LABEL: umin_i64:
436; RV64ZBB:       # %bb.0:
437; RV64ZBB-NEXT:    minu a0, a0, a1
438; RV64ZBB-NEXT:    ret
439  %c = call i64 @llvm.umin.i64(i64 %a, i64 %b)
440  ret i64 %c
441}
442
443; Tests with the same operand used twice. These should fold away.
444
445define signext i32 @smin_same_op_i32(i32 signext %a) {
446; NOZBB-LABEL: smin_same_op_i32:
447; NOZBB:       # %bb.0:
448; NOZBB-NEXT:    ret
449;
450; ZBB-LABEL: smin_same_op_i32:
451; ZBB:       # %bb.0:
452; ZBB-NEXT:    ret
453  %c = call i32 @llvm.smin.i32(i32 %a, i32 %a)
454  ret i32 %c
455}
456
457define signext i32 @smax_same_op_i32(i32 signext %a) {
458; NOZBB-LABEL: smax_same_op_i32:
459; NOZBB:       # %bb.0:
460; NOZBB-NEXT:    ret
461;
462; ZBB-LABEL: smax_same_op_i32:
463; ZBB:       # %bb.0:
464; ZBB-NEXT:    ret
465  %c = call i32 @llvm.smax.i32(i32 %a, i32 %a)
466  ret i32 %c
467}
468
469define signext i32 @umin_same_op_i32(i32 signext %a) {
470; NOZBB-LABEL: umin_same_op_i32:
471; NOZBB:       # %bb.0:
472; NOZBB-NEXT:    ret
473;
474; ZBB-LABEL: umin_same_op_i32:
475; ZBB:       # %bb.0:
476; ZBB-NEXT:    ret
477  %c = call i32 @llvm.umin.i32(i32 %a, i32 %a)
478  ret i32 %c
479}
480
481define signext i32 @umax_same_op_i32(i32 signext %a) {
482; NOZBB-LABEL: umax_same_op_i32:
483; NOZBB:       # %bb.0:
484; NOZBB-NEXT:    ret
485;
486; ZBB-LABEL: umax_same_op_i32:
487; ZBB:       # %bb.0:
488; ZBB-NEXT:    ret
489  %c = call i32 @llvm.umax.i32(i32 %a, i32 %a)
490  ret i32 %c
491}
492
493; Tests with undef operands. These should fold to undef for RV32 or 0 for RV64.
494
495define signext i32 @smin_undef_i32() {
496; RV32I-LABEL: smin_undef_i32:
497; RV32I:       # %bb.0:
498; RV32I-NEXT:    ret
499;
500; RV64I-LABEL: smin_undef_i32:
501; RV64I:       # %bb.0:
502; RV64I-NEXT:    li a0, 0
503; RV64I-NEXT:    ret
504;
505; RV32ZBB-LABEL: smin_undef_i32:
506; RV32ZBB:       # %bb.0:
507; RV32ZBB-NEXT:    ret
508;
509; RV64ZBB-LABEL: smin_undef_i32:
510; RV64ZBB:       # %bb.0:
511; RV64ZBB-NEXT:    li a0, 0
512; RV64ZBB-NEXT:    ret
513  %c = call i32 @llvm.smin.i32(i32 undef, i32 undef)
514  ret i32 %c
515}
516
517define signext i32 @smax_undef_i32() {
518; RV32I-LABEL: smax_undef_i32:
519; RV32I:       # %bb.0:
520; RV32I-NEXT:    ret
521;
522; RV64I-LABEL: smax_undef_i32:
523; RV64I:       # %bb.0:
524; RV64I-NEXT:    li a0, 0
525; RV64I-NEXT:    ret
526;
527; RV32ZBB-LABEL: smax_undef_i32:
528; RV32ZBB:       # %bb.0:
529; RV32ZBB-NEXT:    ret
530;
531; RV64ZBB-LABEL: smax_undef_i32:
532; RV64ZBB:       # %bb.0:
533; RV64ZBB-NEXT:    li a0, 0
534; RV64ZBB-NEXT:    ret
535  %c = call i32 @llvm.smax.i32(i32 undef, i32 undef)
536  ret i32 %c
537}
538
539define signext i32 @umin_undef_i32() {
540; RV32I-LABEL: umin_undef_i32:
541; RV32I:       # %bb.0:
542; RV32I-NEXT:    ret
543;
544; RV64I-LABEL: umin_undef_i32:
545; RV64I:       # %bb.0:
546; RV64I-NEXT:    li a0, 0
547; RV64I-NEXT:    ret
548;
549; RV32ZBB-LABEL: umin_undef_i32:
550; RV32ZBB:       # %bb.0:
551; RV32ZBB-NEXT:    ret
552;
553; RV64ZBB-LABEL: umin_undef_i32:
554; RV64ZBB:       # %bb.0:
555; RV64ZBB-NEXT:    li a0, 0
556; RV64ZBB-NEXT:    ret
557  %c = call i32 @llvm.umin.i32(i32 undef, i32 undef)
558  ret i32 %c
559}
560
561define signext i32 @umax_undef_i32() {
562; RV32I-LABEL: umax_undef_i32:
563; RV32I:       # %bb.0:
564; RV32I-NEXT:    ret
565;
566; RV64I-LABEL: umax_undef_i32:
567; RV64I:       # %bb.0:
568; RV64I-NEXT:    li a0, 0
569; RV64I-NEXT:    ret
570;
571; RV32ZBB-LABEL: umax_undef_i32:
572; RV32ZBB:       # %bb.0:
573; RV32ZBB-NEXT:    ret
574;
575; RV64ZBB-LABEL: umax_undef_i32:
576; RV64ZBB:       # %bb.0:
577; RV64ZBB-NEXT:    li a0, 0
578; RV64ZBB-NEXT:    ret
579  %c = call i32 @llvm.umax.i32(i32 undef, i32 undef)
580  ret i32 %c
581}
582
583define signext i32 @smax_i32_pos_constant(i32 signext %a) {
584; NOZBB-LABEL: smax_i32_pos_constant:
585; NOZBB:       # %bb.0:
586; NOZBB-NEXT:    li a1, 10
587; NOZBB-NEXT:    blt a1, a0, .LBB24_2
588; NOZBB-NEXT:  # %bb.1:
589; NOZBB-NEXT:    li a0, 10
590; NOZBB-NEXT:  .LBB24_2:
591; NOZBB-NEXT:    ret
592;
593; ZBB-LABEL: smax_i32_pos_constant:
594; ZBB:       # %bb.0:
595; ZBB-NEXT:    li a1, 10
596; ZBB-NEXT:    max a0, a0, a1
597; ZBB-NEXT:    ret
598  %c = call i32 @llvm.smax.i32(i32 %a, i32 10)
599  ret i32 %c
600}
601
602define signext i32 @smax_i32_pos_constant_trailing_zeros(i32 signext %a) {
603; NOZBB-LABEL: smax_i32_pos_constant_trailing_zeros:
604; NOZBB:       # %bb.0:
605; NOZBB-NEXT:    andi a0, a0, -8
606; NOZBB-NEXT:    li a1, 16
607; NOZBB-NEXT:    blt a1, a0, .LBB25_2
608; NOZBB-NEXT:  # %bb.1:
609; NOZBB-NEXT:    li a0, 16
610; NOZBB-NEXT:  .LBB25_2:
611; NOZBB-NEXT:    ret
612;
613; ZBB-LABEL: smax_i32_pos_constant_trailing_zeros:
614; ZBB:       # %bb.0:
615; ZBB-NEXT:    andi a0, a0, -8
616; ZBB-NEXT:    li a1, 16
617; ZBB-NEXT:    max a0, a0, a1
618; ZBB-NEXT:    ret
619  %b = and i32 %a, -8
620  %c = call i32 @llvm.smax.i32(i32 %b, i32 16)
621  %d = and i32 %c, -4
622  ret i32 %d
623}
624
625define signext i32 @smin_i32_negone(i32 signext %a) {
626; NOZBB-LABEL: smin_i32_negone:
627; NOZBB:       # %bb.0:
628; NOZBB-NEXT:    slti a1, a0, -1
629; NOZBB-NEXT:    addi a1, a1, -1
630; NOZBB-NEXT:    or a0, a1, a0
631; NOZBB-NEXT:    ret
632;
633; ZBB-LABEL: smin_i32_negone:
634; ZBB:       # %bb.0:
635; ZBB-NEXT:    li a1, -1
636; ZBB-NEXT:    min a0, a0, a1
637; ZBB-NEXT:    ret
638  %c = call i32 @llvm.smin.i32(i32 %a, i32 -1)
639  ret i32 %c
640}
641
642define i64 @smin_i64_negone(i64 %a) {
643; RV32I-LABEL: smin_i64_negone:
644; RV32I:       # %bb.0:
645; RV32I-NEXT:    slti a2, a1, 0
646; RV32I-NEXT:    addi a2, a2, -1
647; RV32I-NEXT:    or a0, a2, a0
648; RV32I-NEXT:    slti a2, a1, -1
649; RV32I-NEXT:    addi a2, a2, -1
650; RV32I-NEXT:    or a1, a2, a1
651; RV32I-NEXT:    ret
652;
653; RV64I-LABEL: smin_i64_negone:
654; RV64I:       # %bb.0:
655; RV64I-NEXT:    slti a1, a0, -1
656; RV64I-NEXT:    addi a1, a1, -1
657; RV64I-NEXT:    or a0, a1, a0
658; RV64I-NEXT:    ret
659;
660; RV32ZBB-LABEL: smin_i64_negone:
661; RV32ZBB:       # %bb.0:
662; RV32ZBB-NEXT:    li a2, -1
663; RV32ZBB-NEXT:    min a2, a1, a2
664; RV32ZBB-NEXT:    slti a1, a1, 0
665; RV32ZBB-NEXT:    addi a1, a1, -1
666; RV32ZBB-NEXT:    or a0, a1, a0
667; RV32ZBB-NEXT:    mv a1, a2
668; RV32ZBB-NEXT:    ret
669;
670; RV64ZBB-LABEL: smin_i64_negone:
671; RV64ZBB:       # %bb.0:
672; RV64ZBB-NEXT:    li a1, -1
673; RV64ZBB-NEXT:    min a0, a0, a1
674; RV64ZBB-NEXT:    ret
675  %c = call i64 @llvm.smin.i64(i64 %a, i64 -1)
676  ret i64 %c
677}
678
679define i64 @umax_i64_one(i64 %a, i64 %b) {
680; RV32I-LABEL: umax_i64_one:
681; RV32I:       # %bb.0:
682; RV32I-NEXT:    mv a2, a0
683; RV32I-NEXT:    beqz a1, .LBB28_3
684; RV32I-NEXT:  # %bb.1:
685; RV32I-NEXT:    beqz a1, .LBB28_4
686; RV32I-NEXT:  .LBB28_2:
687; RV32I-NEXT:    ret
688; RV32I-NEXT:  .LBB28_3:
689; RV32I-NEXT:    li a0, 1
690; RV32I-NEXT:    bnez a1, .LBB28_2
691; RV32I-NEXT:  .LBB28_4:
692; RV32I-NEXT:    seqz a0, a2
693; RV32I-NEXT:    add a0, a2, a0
694; RV32I-NEXT:    ret
695;
696; RV64I-LABEL: umax_i64_one:
697; RV64I:       # %bb.0:
698; RV64I-NEXT:    seqz a1, a0
699; RV64I-NEXT:    add a0, a0, a1
700; RV64I-NEXT:    ret
701;
702; RV32ZBB-LABEL: umax_i64_one:
703; RV32ZBB:       # %bb.0:
704; RV32ZBB-NEXT:    mv a2, a0
705; RV32ZBB-NEXT:    li a3, 1
706; RV32ZBB-NEXT:    beqz a1, .LBB28_3
707; RV32ZBB-NEXT:  # %bb.1:
708; RV32ZBB-NEXT:    beqz a1, .LBB28_4
709; RV32ZBB-NEXT:  .LBB28_2:
710; RV32ZBB-NEXT:    ret
711; RV32ZBB-NEXT:  .LBB28_3:
712; RV32ZBB-NEXT:    li a0, 1
713; RV32ZBB-NEXT:    bnez a1, .LBB28_2
714; RV32ZBB-NEXT:  .LBB28_4:
715; RV32ZBB-NEXT:    maxu a0, a2, a3
716; RV32ZBB-NEXT:    ret
717;
718; RV64ZBB-LABEL: umax_i64_one:
719; RV64ZBB:       # %bb.0:
720; RV64ZBB-NEXT:    li a1, 1
721; RV64ZBB-NEXT:    maxu a0, a0, a1
722; RV64ZBB-NEXT:    ret
723  %c = call i64 @llvm.umax.i64(i64 %a, i64 1)
724  ret i64 %c
725}
726