xref: /llvm-project/llvm/test/CodeGen/RISCV/mem.ll (revision eabaee0c59110d0e11b33a69db54ccda526b35fd)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV32I
4
5; Check indexed and unindexed, sext, zext and anyext loads
6
7define dso_local i32 @lb(ptr %a) nounwind {
8; RV32I-LABEL: lb:
9; RV32I:       # %bb.0:
10; RV32I-NEXT:    lb a1, 1(a0)
11; RV32I-NEXT:    lbu zero, 0(a0)
12; RV32I-NEXT:    mv a0, a1
13; RV32I-NEXT:    ret
14  %1 = getelementptr i8, ptr %a, i32 1
15  %2 = load i8, ptr %1
16  %3 = sext i8 %2 to i32
17  ; the unused load will produce an anyext for selection
18  %4 = load volatile i8, ptr %a
19  ret i32 %3
20}
21
22define dso_local i32 @lh(ptr %a) nounwind {
23; RV32I-LABEL: lh:
24; RV32I:       # %bb.0:
25; RV32I-NEXT:    lh a1, 4(a0)
26; RV32I-NEXT:    lh zero, 0(a0)
27; RV32I-NEXT:    mv a0, a1
28; RV32I-NEXT:    ret
29  %1 = getelementptr i16, ptr %a, i32 2
30  %2 = load i16, ptr %1
31  %3 = sext i16 %2 to i32
32  ; the unused load will produce an anyext for selection
33  %4 = load volatile i16, ptr %a
34  ret i32 %3
35}
36
37define dso_local i32 @lw(ptr %a) nounwind {
38; RV32I-LABEL: lw:
39; RV32I:       # %bb.0:
40; RV32I-NEXT:    lw a1, 12(a0)
41; RV32I-NEXT:    lw zero, 0(a0)
42; RV32I-NEXT:    mv a0, a1
43; RV32I-NEXT:    ret
44  %1 = getelementptr i32, ptr %a, i32 3
45  %2 = load i32, ptr %1
46  %3 = load volatile i32, ptr %a
47  ret i32 %2
48}
49
50define dso_local i32 @lbu(ptr %a) nounwind {
51; RV32I-LABEL: lbu:
52; RV32I:       # %bb.0:
53; RV32I-NEXT:    lbu a1, 4(a0)
54; RV32I-NEXT:    lbu a0, 0(a0)
55; RV32I-NEXT:    add a0, a1, a0
56; RV32I-NEXT:    ret
57  %1 = getelementptr i8, ptr %a, i32 4
58  %2 = load i8, ptr %1
59  %3 = zext i8 %2 to i32
60  %4 = load volatile i8, ptr %a
61  %5 = zext i8 %4 to i32
62  %6 = add i32 %3, %5
63  ret i32 %6
64}
65
66define dso_local i32 @lhu(ptr %a) nounwind {
67; RV32I-LABEL: lhu:
68; RV32I:       # %bb.0:
69; RV32I-NEXT:    lhu a1, 10(a0)
70; RV32I-NEXT:    lhu a0, 0(a0)
71; RV32I-NEXT:    add a0, a1, a0
72; RV32I-NEXT:    ret
73  %1 = getelementptr i16, ptr %a, i32 5
74  %2 = load i16, ptr %1
75  %3 = zext i16 %2 to i32
76  %4 = load volatile i16, ptr %a
77  %5 = zext i16 %4 to i32
78  %6 = add i32 %3, %5
79  ret i32 %6
80}
81
82; Check indexed and unindexed stores
83
84define dso_local void @sb(ptr %a, i8 %b) nounwind {
85; RV32I-LABEL: sb:
86; RV32I:       # %bb.0:
87; RV32I-NEXT:    sb a1, 0(a0)
88; RV32I-NEXT:    sb a1, 6(a0)
89; RV32I-NEXT:    ret
90  store i8 %b, ptr %a
91  %1 = getelementptr i8, ptr %a, i32 6
92  store i8 %b, ptr %1
93  ret void
94}
95
96define dso_local void @sh(ptr %a, i16 %b) nounwind {
97; RV32I-LABEL: sh:
98; RV32I:       # %bb.0:
99; RV32I-NEXT:    sh a1, 0(a0)
100; RV32I-NEXT:    sh a1, 14(a0)
101; RV32I-NEXT:    ret
102  store i16 %b, ptr %a
103  %1 = getelementptr i16, ptr %a, i32 7
104  store i16 %b, ptr %1
105  ret void
106}
107
108define dso_local void @sw(ptr %a, i32 %b) nounwind {
109; RV32I-LABEL: sw:
110; RV32I:       # %bb.0:
111; RV32I-NEXT:    sw a1, 0(a0)
112; RV32I-NEXT:    sw a1, 32(a0)
113; RV32I-NEXT:    ret
114  store i32 %b, ptr %a
115  %1 = getelementptr i32, ptr %a, i32 8
116  store i32 %b, ptr %1
117  ret void
118}
119
120; Check load and store to an i1 location
121define dso_local i32 @load_sext_zext_anyext_i1(ptr %a) nounwind {
122; RV32I-LABEL: load_sext_zext_anyext_i1:
123; RV32I:       # %bb.0:
124; RV32I-NEXT:    lbu a1, 1(a0)
125; RV32I-NEXT:    lbu a2, 2(a0)
126; RV32I-NEXT:    lbu zero, 0(a0)
127; RV32I-NEXT:    sub a0, a2, a1
128; RV32I-NEXT:    ret
129  ; sextload i1
130  %1 = getelementptr i1, ptr %a, i32 1
131  %2 = load i1, ptr %1
132  %3 = sext i1 %2 to i32
133  ; zextload i1
134  %4 = getelementptr i1, ptr %a, i32 2
135  %5 = load i1, ptr %4
136  %6 = zext i1 %5 to i32
137  %7 = add i32 %3, %6
138  ; extload i1 (anyext). Produced as the load is unused.
139  %8 = load volatile i1, ptr %a
140  ret i32 %7
141}
142
143define dso_local i16 @load_sext_zext_anyext_i1_i16(ptr %a) nounwind {
144; RV32I-LABEL: load_sext_zext_anyext_i1_i16:
145; RV32I:       # %bb.0:
146; RV32I-NEXT:    lbu a1, 1(a0)
147; RV32I-NEXT:    lbu a2, 2(a0)
148; RV32I-NEXT:    lbu zero, 0(a0)
149; RV32I-NEXT:    sub a0, a2, a1
150; RV32I-NEXT:    ret
151  ; sextload i1
152  %1 = getelementptr i1, ptr %a, i32 1
153  %2 = load i1, ptr %1
154  %3 = sext i1 %2 to i16
155  ; zextload i1
156  %4 = getelementptr i1, ptr %a, i32 2
157  %5 = load i1, ptr %4
158  %6 = zext i1 %5 to i16
159  %7 = add i16 %3, %6
160  ; extload i1 (anyext). Produced as the load is unused.
161  %8 = load volatile i1, ptr %a
162  ret i16 %7
163}
164
165; Check load and store to a global
166@G = dso_local global i32 0
167
168define dso_local i32 @lw_sw_global(i32 %a) nounwind {
169; RV32I-LABEL: lw_sw_global:
170; RV32I:       # %bb.0:
171; RV32I-NEXT:    lui a2, %hi(G)
172; RV32I-NEXT:    lw a1, %lo(G)(a2)
173; RV32I-NEXT:    addi a3, a2, %lo(G)
174; RV32I-NEXT:    sw a0, %lo(G)(a2)
175; RV32I-NEXT:    lw zero, 36(a3)
176; RV32I-NEXT:    sw a0, 36(a3)
177; RV32I-NEXT:    mv a0, a1
178; RV32I-NEXT:    ret
179  %1 = load volatile i32, ptr @G
180  store i32 %a, ptr @G
181  %2 = getelementptr i32, ptr @G, i32 9
182  %3 = load volatile i32, ptr %2
183  store i32 %a, ptr %2
184  ret i32 %1
185}
186
187; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1
188define dso_local i32 @lw_sw_constant(i32 %a) nounwind {
189; RV32I-LABEL: lw_sw_constant:
190; RV32I:       # %bb.0:
191; RV32I-NEXT:    lui a2, 912092
192; RV32I-NEXT:    lw a1, -273(a2)
193; RV32I-NEXT:    sw a0, -273(a2)
194; RV32I-NEXT:    mv a0, a1
195; RV32I-NEXT:    ret
196  %1 = inttoptr i32 3735928559 to ptr
197  %2 = load volatile i32, ptr %1
198  store i32 %a, ptr %1
199  ret i32 %2
200}
201
202define i32 @lw_near_local(ptr %a)  {
203; RV32I-LABEL: lw_near_local:
204; RV32I:       # %bb.0:
205; RV32I-NEXT:    addi a0, a0, 2047
206; RV32I-NEXT:    lw a0, 5(a0)
207; RV32I-NEXT:    ret
208  %1 = getelementptr inbounds i32, ptr %a, i64 513
209  %2 = load volatile i32, ptr %1
210  ret i32 %2
211}
212
213define void @st_near_local(ptr %a, i32 %b)  {
214; RV32I-LABEL: st_near_local:
215; RV32I:       # %bb.0:
216; RV32I-NEXT:    addi a0, a0, 2047
217; RV32I-NEXT:    sw a1, 5(a0)
218; RV32I-NEXT:    ret
219  %1 = getelementptr inbounds i32, ptr %a, i64 513
220  store i32 %b, ptr %1
221  ret void
222}
223
224define i32 @lw_sw_near_local(ptr %a, i32 %b)  {
225; RV32I-LABEL: lw_sw_near_local:
226; RV32I:       # %bb.0:
227; RV32I-NEXT:    addi a2, a0, 2047
228; RV32I-NEXT:    lw a0, 5(a2)
229; RV32I-NEXT:    sw a1, 5(a2)
230; RV32I-NEXT:    ret
231  %1 = getelementptr inbounds i32, ptr %a, i64 513
232  %2 = load volatile i32, ptr %1
233  store i32 %b, ptr %1
234  ret i32 %2
235}
236
237define i32 @lw_far_local(ptr %a)  {
238; RV32I-LABEL: lw_far_local:
239; RV32I:       # %bb.0:
240; RV32I-NEXT:    lui a1, 4
241; RV32I-NEXT:    add a0, a0, a1
242; RV32I-NEXT:    lw a0, -4(a0)
243; RV32I-NEXT:    ret
244  %1 = getelementptr inbounds i32, ptr %a, i64 4095
245  %2 = load volatile i32, ptr %1
246  ret i32 %2
247}
248
249define void @st_far_local(ptr %a, i32 %b)  {
250; RV32I-LABEL: st_far_local:
251; RV32I:       # %bb.0:
252; RV32I-NEXT:    lui a2, 4
253; RV32I-NEXT:    add a0, a0, a2
254; RV32I-NEXT:    sw a1, -4(a0)
255; RV32I-NEXT:    ret
256  %1 = getelementptr inbounds i32, ptr %a, i64 4095
257  store i32 %b, ptr %1
258  ret void
259}
260
261define i32 @lw_sw_far_local(ptr %a, i32 %b)  {
262; RV32I-LABEL: lw_sw_far_local:
263; RV32I:       # %bb.0:
264; RV32I-NEXT:    lui a2, 4
265; RV32I-NEXT:    add a2, a0, a2
266; RV32I-NEXT:    lw a0, -4(a2)
267; RV32I-NEXT:    sw a1, -4(a2)
268; RV32I-NEXT:    ret
269  %1 = getelementptr inbounds i32, ptr %a, i64 4095
270  %2 = load volatile i32, ptr %1
271  store i32 %b, ptr %1
272  ret i32 %2
273}
274
275define i32 @lw_really_far_local(ptr %a)  {
276; RV32I-LABEL: lw_really_far_local:
277; RV32I:       # %bb.0:
278; RV32I-NEXT:    lui a1, 524288
279; RV32I-NEXT:    add a0, a0, a1
280; RV32I-NEXT:    lw a0, -2048(a0)
281; RV32I-NEXT:    ret
282  %1 = getelementptr inbounds i32, ptr %a, i32 536870400
283  %2 = load volatile i32, ptr %1
284  ret i32 %2
285}
286
287define void @st_really_far_local(ptr %a, i32 %b)  {
288; RV32I-LABEL: st_really_far_local:
289; RV32I:       # %bb.0:
290; RV32I-NEXT:    lui a2, 524288
291; RV32I-NEXT:    add a0, a0, a2
292; RV32I-NEXT:    sw a1, -2048(a0)
293; RV32I-NEXT:    ret
294  %1 = getelementptr inbounds i32, ptr %a, i32 536870400
295  store i32 %b, ptr %1
296  ret void
297}
298
299define i32 @lw_sw_really_far_local(ptr %a, i32 %b)  {
300; RV32I-LABEL: lw_sw_really_far_local:
301; RV32I:       # %bb.0:
302; RV32I-NEXT:    lui a2, 524288
303; RV32I-NEXT:    add a2, a0, a2
304; RV32I-NEXT:    lw a0, -2048(a2)
305; RV32I-NEXT:    sw a1, -2048(a2)
306; RV32I-NEXT:    ret
307  %1 = getelementptr inbounds i32, ptr %a, i32 536870400
308  %2 = load volatile i32, ptr %1
309  store i32 %b, ptr %1
310  ret i32 %2
311}
312
313%struct.quux = type { i32, [0 x i8] }
314
315; Make sure we don't remove the addi and fold the C from
316; (add (addi FrameIndex, C), X) into the store address.
317; FrameIndex cannot be the operand of an ADD. We must keep the ADDI.
318define void @addi_fold_crash(i32 %arg) nounwind {
319; RV32I-LABEL: addi_fold_crash:
320; RV32I:       # %bb.0: # %bb
321; RV32I-NEXT:    addi sp, sp, -16
322; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
323; RV32I-NEXT:    addi a1, sp, 12
324; RV32I-NEXT:    add a0, a1, a0
325; RV32I-NEXT:    sb zero, 0(a0)
326; RV32I-NEXT:    mv a0, a1
327; RV32I-NEXT:    call snork
328; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
329; RV32I-NEXT:    addi sp, sp, 16
330; RV32I-NEXT:    ret
331bb:
332  %tmp = alloca %struct.quux, align 4
333  %tmp1 = getelementptr inbounds %struct.quux, ptr %tmp, i32 0, i32 1
334  %tmp2 = getelementptr inbounds %struct.quux, ptr %tmp, i32 0, i32 1, i32 %arg
335  store i8 0, ptr %tmp2, align 1
336  call void @snork(ptr %tmp1)
337  ret void
338}
339
340declare void @snork(ptr)
341
342define i8 @disjoint_or_lb(ptr %a, i32 %off) nounwind {
343; RV32I-LABEL: disjoint_or_lb:
344; RV32I:       # %bb.0:
345; RV32I-NEXT:    add a0, a0, a1
346; RV32I-NEXT:    lbu a0, 3(a0)
347; RV32I-NEXT:    ret
348  %b = or disjoint i32 %off, 3
349  %1 = getelementptr i8, ptr %a, i32 %b
350  %2 = load i8, ptr %1
351  ret i8 %2
352}
353
354define i32 @disjoint_or_lw(ptr %a, i32 %off) nounwind {
355; RV32I-LABEL: disjoint_or_lw:
356; RV32I:       # %bb.0:
357; RV32I-NEXT:    slli a1, a1, 2
358; RV32I-NEXT:    add a0, a0, a1
359; RV32I-NEXT:    lw a0, 12(a0)
360; RV32I-NEXT:    ret
361  %b = or disjoint i32 %off, 3
362  %1 = getelementptr i32, ptr %a, i32 %b
363  %2 = load i32, ptr %1
364  ret i32 %2
365}
366