xref: /llvm-project/llvm/test/CodeGen/RISCV/machine-cse.ll (revision 40f1af47601044149102b1597d5f56689661f8a5)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32
3; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefixes=RV64
4
5; Make sure MachineCSE can combine the adds with the operands commuted.
6
7define void @commute_add_i32(i32 signext %x, i32 signext %y, i32* %p1, i32* %p2, i1 zeroext %cond) {
8; RV32-LABEL: commute_add_i32:
9; RV32:       # %bb.0:
10; RV32-NEXT:    add a0, a0, a1
11; RV32-NEXT:    sw a0, 0(a2)
12; RV32-NEXT:    beqz a4, .LBB0_2
13; RV32-NEXT:  # %bb.1: # %trueblock
14; RV32-NEXT:    sw a0, 0(a2)
15; RV32-NEXT:  .LBB0_2: # %falseblock
16; RV32-NEXT:    ret
17;
18; RV64-LABEL: commute_add_i32:
19; RV64:       # %bb.0:
20; RV64-NEXT:    addw a0, a0, a1
21; RV64-NEXT:    sw a0, 0(a2)
22; RV64-NEXT:    beqz a4, .LBB0_2
23; RV64-NEXT:  # %bb.1: # %trueblock
24; RV64-NEXT:    sw a0, 0(a2)
25; RV64-NEXT:  .LBB0_2: # %falseblock
26; RV64-NEXT:    ret
27  %a = add i32 %x, %y
28  store i32 %a, i32* %p1
29  br i1 %cond, label %trueblock, label %falseblock
30
31trueblock:
32  %b = add i32 %y, %x
33  store i32 %b, i32* %p1
34  br label %falseblock
35
36falseblock:
37  ret void
38}
39
40define void @commute_add_i64(i64 %x, i64 %y, i64* %p1, i64* %p2, i1 zeroext %cond) {
41; RV32-LABEL: commute_add_i64:
42; RV32:       # %bb.0:
43; RV32-NEXT:    add a1, a1, a3
44; RV32-NEXT:    add a3, a0, a2
45; RV32-NEXT:    sltu a0, a3, a0
46; RV32-NEXT:    add a0, a1, a0
47; RV32-NEXT:    sw a3, 0(a4)
48; RV32-NEXT:    sw a0, 4(a4)
49; RV32-NEXT:    beqz a6, .LBB1_2
50; RV32-NEXT:  # %bb.1: # %trueblock
51; RV32-NEXT:    sltu a0, a3, a2
52; RV32-NEXT:    add a0, a1, a0
53; RV32-NEXT:    sw a3, 0(a4)
54; RV32-NEXT:    sw a0, 4(a4)
55; RV32-NEXT:  .LBB1_2: # %falseblock
56; RV32-NEXT:    ret
57;
58; RV64-LABEL: commute_add_i64:
59; RV64:       # %bb.0:
60; RV64-NEXT:    add a0, a0, a1
61; RV64-NEXT:    sd a0, 0(a2)
62; RV64-NEXT:    beqz a4, .LBB1_2
63; RV64-NEXT:  # %bb.1: # %trueblock
64; RV64-NEXT:    sd a0, 0(a2)
65; RV64-NEXT:  .LBB1_2: # %falseblock
66; RV64-NEXT:    ret
67  %a = add i64 %x, %y
68  store i64 %a, i64* %p1
69  br i1 %cond, label %trueblock, label %falseblock
70
71trueblock:
72  %b = add i64 %y, %x
73  store i64 %b, i64* %p1
74  br label %falseblock
75
76falseblock:
77  ret void
78}
79