1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=riscv32 -mattr=+f,+d,+zfh -target-abi=ilp32d | \ 3; RUN: FileCheck %s --check-prefixes=RV32 4; RUN: llc < %s -mtriple=riscv64 -mattr=+f,+d,+zfh -target-abi=lp64d | \ 5; RUN: FileCheck %s --check-prefixes=RV64 6 7; Make sure MachineCSE can combine the adds with the operands commuted. 8 9define void @commute_add_i32(i32 signext %x, i32 signext %y, ptr %p1, ptr %p2, i1 zeroext %cond) { 10; RV32-LABEL: commute_add_i32: 11; RV32: # %bb.0: 12; RV32-NEXT: add a0, a0, a1 13; RV32-NEXT: sw a0, 0(a2) 14; RV32-NEXT: beqz a4, .LBB0_2 15; RV32-NEXT: # %bb.1: # %trueblock 16; RV32-NEXT: sw a0, 0(a2) 17; RV32-NEXT: .LBB0_2: # %falseblock 18; RV32-NEXT: ret 19; 20; RV64-LABEL: commute_add_i32: 21; RV64: # %bb.0: 22; RV64-NEXT: add a0, a0, a1 23; RV64-NEXT: sw a0, 0(a2) 24; RV64-NEXT: beqz a4, .LBB0_2 25; RV64-NEXT: # %bb.1: # %trueblock 26; RV64-NEXT: sw a0, 0(a2) 27; RV64-NEXT: .LBB0_2: # %falseblock 28; RV64-NEXT: ret 29 %a = add i32 %x, %y 30 store i32 %a, ptr %p1 31 br i1 %cond, label %trueblock, label %falseblock 32 33trueblock: 34 %b = add i32 %y, %x 35 store i32 %b, ptr %p1 36 br label %falseblock 37 38falseblock: 39 ret void 40} 41 42define void @commute_add_i64(i64 %x, i64 %y, ptr %p1, ptr %p2, i1 zeroext %cond) { 43; RV32-LABEL: commute_add_i64: 44; RV32: # %bb.0: 45; RV32-NEXT: add a1, a1, a3 46; RV32-NEXT: add a3, a0, a2 47; RV32-NEXT: sltu a0, a3, a0 48; RV32-NEXT: add a0, a1, a0 49; RV32-NEXT: sw a3, 0(a4) 50; RV32-NEXT: sw a0, 4(a4) 51; RV32-NEXT: beqz a6, .LBB1_2 52; RV32-NEXT: # %bb.1: # %trueblock 53; RV32-NEXT: sltu a0, a3, a2 54; RV32-NEXT: add a0, a1, a0 55; RV32-NEXT: sw a3, 0(a4) 56; RV32-NEXT: sw a0, 4(a4) 57; RV32-NEXT: .LBB1_2: # %falseblock 58; RV32-NEXT: ret 59; 60; RV64-LABEL: commute_add_i64: 61; RV64: # %bb.0: 62; RV64-NEXT: add a0, a0, a1 63; RV64-NEXT: sd a0, 0(a2) 64; RV64-NEXT: beqz a4, .LBB1_2 65; RV64-NEXT: # %bb.1: # %trueblock 66; RV64-NEXT: sd a0, 0(a2) 67; RV64-NEXT: .LBB1_2: # %falseblock 68; RV64-NEXT: ret 69 %a = add i64 %x, %y 70 store i64 %a, ptr %p1 71 br i1 %cond, label %trueblock, label %falseblock 72 73trueblock: 74 %b = add i64 %y, %x 75 store i64 %b, ptr %p1 76 br label %falseblock 77 78falseblock: 79 ret void 80} 81 82declare half @llvm.fma.f16(half, half, half) 83 84define void @commute_fmadd_f16(half %x, half %y, half %z, ptr %p1, ptr %p2, i1 zeroext %cond) { 85; RV32-LABEL: commute_fmadd_f16: 86; RV32: # %bb.0: 87; RV32-NEXT: fmadd.h fa5, fa0, fa1, fa2 88; RV32-NEXT: fsh fa5, 0(a0) 89; RV32-NEXT: beqz a2, .LBB2_2 90; RV32-NEXT: # %bb.1: # %trueblock 91; RV32-NEXT: fsh fa5, 0(a0) 92; RV32-NEXT: .LBB2_2: # %falseblock 93; RV32-NEXT: ret 94; 95; RV64-LABEL: commute_fmadd_f16: 96; RV64: # %bb.0: 97; RV64-NEXT: fmadd.h fa5, fa0, fa1, fa2 98; RV64-NEXT: fsh fa5, 0(a0) 99; RV64-NEXT: beqz a2, .LBB2_2 100; RV64-NEXT: # %bb.1: # %trueblock 101; RV64-NEXT: fsh fa5, 0(a0) 102; RV64-NEXT: .LBB2_2: # %falseblock 103; RV64-NEXT: ret 104 %a = call half @llvm.fma.f16(half %x, half %y, half %z) 105 store half %a, ptr %p1 106 br i1 %cond, label %trueblock, label %falseblock 107 108trueblock: 109 %b = call half @llvm.fma.f16(half %y, half %x, half %z) 110 store half %b, ptr %p1 111 br label %falseblock 112 113falseblock: 114 ret void 115} 116 117declare float @llvm.fma.f32(float, float, float) 118 119define void @commute_fmadd_f32(float %x, float %y, float %z, ptr %p1, ptr %p2, i1 zeroext %cond) { 120; RV32-LABEL: commute_fmadd_f32: 121; RV32: # %bb.0: 122; RV32-NEXT: fmadd.s fa5, fa0, fa1, fa2 123; RV32-NEXT: fsw fa5, 0(a0) 124; RV32-NEXT: beqz a2, .LBB3_2 125; RV32-NEXT: # %bb.1: # %trueblock 126; RV32-NEXT: fsw fa5, 0(a0) 127; RV32-NEXT: .LBB3_2: # %falseblock 128; RV32-NEXT: ret 129; 130; RV64-LABEL: commute_fmadd_f32: 131; RV64: # %bb.0: 132; RV64-NEXT: fmadd.s fa5, fa0, fa1, fa2 133; RV64-NEXT: fsw fa5, 0(a0) 134; RV64-NEXT: beqz a2, .LBB3_2 135; RV64-NEXT: # %bb.1: # %trueblock 136; RV64-NEXT: fsw fa5, 0(a0) 137; RV64-NEXT: .LBB3_2: # %falseblock 138; RV64-NEXT: ret 139 %a = call float @llvm.fma.f32(float %x, float %y, float %z) 140 store float %a, ptr %p1 141 br i1 %cond, label %trueblock, label %falseblock 142 143trueblock: 144 %b = call float @llvm.fma.f32(float %y, float %x, float %z) 145 store float %b, ptr %p1 146 br label %falseblock 147 148falseblock: 149 ret void 150} 151 152declare double @llvm.fma.f64(double, double, double) 153 154define void @commute_fmadd_f64(double %x, double %y, double %z, ptr %p1, ptr %p2, i1 zeroext %cond) { 155; RV32-LABEL: commute_fmadd_f64: 156; RV32: # %bb.0: 157; RV32-NEXT: fmadd.d fa5, fa0, fa1, fa2 158; RV32-NEXT: fsd fa5, 0(a0) 159; RV32-NEXT: beqz a2, .LBB4_2 160; RV32-NEXT: # %bb.1: # %trueblock 161; RV32-NEXT: fsd fa5, 0(a0) 162; RV32-NEXT: .LBB4_2: # %falseblock 163; RV32-NEXT: ret 164; 165; RV64-LABEL: commute_fmadd_f64: 166; RV64: # %bb.0: 167; RV64-NEXT: fmadd.d fa5, fa0, fa1, fa2 168; RV64-NEXT: fsd fa5, 0(a0) 169; RV64-NEXT: beqz a2, .LBB4_2 170; RV64-NEXT: # %bb.1: # %trueblock 171; RV64-NEXT: fsd fa5, 0(a0) 172; RV64-NEXT: .LBB4_2: # %falseblock 173; RV64-NEXT: ret 174 %a = call double @llvm.fma.f64(double %x, double %y, double %z) 175 store double %a, ptr %p1 176 br i1 %cond, label %trueblock, label %falseblock 177 178trueblock: 179 %b = call double @llvm.fma.f64(double %y, double %x, double %z) 180 store double %b, ptr %p1 181 br label %falseblock 182 183falseblock: 184 ret void 185} 186 187define void @commute_fmsub_f16(half %x, half %y, half %z, ptr %p1, ptr %p2, i1 zeroext %cond) { 188; RV32-LABEL: commute_fmsub_f16: 189; RV32: # %bb.0: 190; RV32-NEXT: fmsub.h fa5, fa0, fa1, fa2 191; RV32-NEXT: fsh fa5, 0(a0) 192; RV32-NEXT: beqz a2, .LBB5_2 193; RV32-NEXT: # %bb.1: # %trueblock 194; RV32-NEXT: fsh fa5, 0(a0) 195; RV32-NEXT: .LBB5_2: # %falseblock 196; RV32-NEXT: ret 197; 198; RV64-LABEL: commute_fmsub_f16: 199; RV64: # %bb.0: 200; RV64-NEXT: fmsub.h fa5, fa0, fa1, fa2 201; RV64-NEXT: fsh fa5, 0(a0) 202; RV64-NEXT: beqz a2, .LBB5_2 203; RV64-NEXT: # %bb.1: # %trueblock 204; RV64-NEXT: fsh fa5, 0(a0) 205; RV64-NEXT: .LBB5_2: # %falseblock 206; RV64-NEXT: ret 207 %negz = fneg half %z 208 %a = call half @llvm.fma.f16(half %x, half %y, half %negz) 209 store half %a, ptr %p1 210 br i1 %cond, label %trueblock, label %falseblock 211 212trueblock: 213 %negz2 = fneg half %z 214 %b = call half @llvm.fma.f16(half %y, half %x, half %negz2) 215 store half %b, ptr %p1 216 br label %falseblock 217 218falseblock: 219 ret void 220} 221 222define void @commute_fmsub_f32(float %x, float %y, float %z, ptr %p1, ptr %p2, i1 zeroext %cond) { 223; RV32-LABEL: commute_fmsub_f32: 224; RV32: # %bb.0: 225; RV32-NEXT: fmsub.s fa5, fa0, fa1, fa2 226; RV32-NEXT: fsw fa5, 0(a0) 227; RV32-NEXT: beqz a2, .LBB6_2 228; RV32-NEXT: # %bb.1: # %trueblock 229; RV32-NEXT: fsw fa5, 0(a0) 230; RV32-NEXT: .LBB6_2: # %falseblock 231; RV32-NEXT: ret 232; 233; RV64-LABEL: commute_fmsub_f32: 234; RV64: # %bb.0: 235; RV64-NEXT: fmsub.s fa5, fa0, fa1, fa2 236; RV64-NEXT: fsw fa5, 0(a0) 237; RV64-NEXT: beqz a2, .LBB6_2 238; RV64-NEXT: # %bb.1: # %trueblock 239; RV64-NEXT: fsw fa5, 0(a0) 240; RV64-NEXT: .LBB6_2: # %falseblock 241; RV64-NEXT: ret 242 %negz = fneg float %z 243 %a = call float @llvm.fma.f32(float %x, float %y, float %negz) 244 store float %a, ptr %p1 245 br i1 %cond, label %trueblock, label %falseblock 246 247trueblock: 248 %negz2 = fneg float %z 249 %b = call float @llvm.fma.f32(float %y, float %x, float %negz2) 250 store float %b, ptr %p1 251 br label %falseblock 252 253falseblock: 254 ret void 255} 256 257define void @commute_fmsub_f64(double %x, double %y, double %z, ptr %p1, ptr %p2, i1 zeroext %cond) { 258; RV32-LABEL: commute_fmsub_f64: 259; RV32: # %bb.0: 260; RV32-NEXT: fmsub.d fa5, fa0, fa1, fa2 261; RV32-NEXT: fsd fa5, 0(a0) 262; RV32-NEXT: beqz a2, .LBB7_2 263; RV32-NEXT: # %bb.1: # %trueblock 264; RV32-NEXT: fsd fa5, 0(a0) 265; RV32-NEXT: .LBB7_2: # %falseblock 266; RV32-NEXT: ret 267; 268; RV64-LABEL: commute_fmsub_f64: 269; RV64: # %bb.0: 270; RV64-NEXT: fmsub.d fa5, fa0, fa1, fa2 271; RV64-NEXT: fsd fa5, 0(a0) 272; RV64-NEXT: beqz a2, .LBB7_2 273; RV64-NEXT: # %bb.1: # %trueblock 274; RV64-NEXT: fsd fa5, 0(a0) 275; RV64-NEXT: .LBB7_2: # %falseblock 276; RV64-NEXT: ret 277 %negz = fneg double %z 278 %a = call double @llvm.fma.f64(double %x, double %y, double %negz) 279 store double %a, ptr %p1 280 br i1 %cond, label %trueblock, label %falseblock 281 282trueblock: 283 %negz2 = fneg double %z 284 %b = call double @llvm.fma.f64(double %y, double %x, double %negz2) 285 store double %b, ptr %p1 286 br label %falseblock 287 288falseblock: 289 ret void 290} 291 292define void @commute_fnmadd_f16(half %x, half %y, half %z, ptr %p1, ptr %p2, i1 zeroext %cond) { 293; RV32-LABEL: commute_fnmadd_f16: 294; RV32: # %bb.0: 295; RV32-NEXT: fnmadd.h fa5, fa0, fa1, fa2 296; RV32-NEXT: fsh fa5, 0(a0) 297; RV32-NEXT: beqz a2, .LBB8_2 298; RV32-NEXT: # %bb.1: # %trueblock 299; RV32-NEXT: fsh fa5, 0(a0) 300; RV32-NEXT: .LBB8_2: # %falseblock 301; RV32-NEXT: ret 302; 303; RV64-LABEL: commute_fnmadd_f16: 304; RV64: # %bb.0: 305; RV64-NEXT: fnmadd.h fa5, fa0, fa1, fa2 306; RV64-NEXT: fsh fa5, 0(a0) 307; RV64-NEXT: beqz a2, .LBB8_2 308; RV64-NEXT: # %bb.1: # %trueblock 309; RV64-NEXT: fsh fa5, 0(a0) 310; RV64-NEXT: .LBB8_2: # %falseblock 311; RV64-NEXT: ret 312 %negx = fneg half %x 313 %negz = fneg half %z 314 %a = call half @llvm.fma.f16(half %negx, half %y, half %negz) 315 store half %a, ptr %p1 316 br i1 %cond, label %trueblock, label %falseblock 317 318trueblock: 319 %negy = fneg half %y 320 %negz2 = fneg half %z 321 %b = call half @llvm.fma.f16(half %negy, half %x, half %negz2) 322 store half %b, ptr %p1 323 br label %falseblock 324 325falseblock: 326 ret void 327} 328 329define void @commute_fnmadd_f32(float %x, float %y, float %z, ptr %p1, ptr %p2, i1 zeroext %cond) { 330; RV32-LABEL: commute_fnmadd_f32: 331; RV32: # %bb.0: 332; RV32-NEXT: fnmadd.s fa5, fa0, fa1, fa2 333; RV32-NEXT: fsw fa5, 0(a0) 334; RV32-NEXT: beqz a2, .LBB9_2 335; RV32-NEXT: # %bb.1: # %trueblock 336; RV32-NEXT: fsw fa5, 0(a0) 337; RV32-NEXT: .LBB9_2: # %falseblock 338; RV32-NEXT: ret 339; 340; RV64-LABEL: commute_fnmadd_f32: 341; RV64: # %bb.0: 342; RV64-NEXT: fnmadd.s fa5, fa0, fa1, fa2 343; RV64-NEXT: fsw fa5, 0(a0) 344; RV64-NEXT: beqz a2, .LBB9_2 345; RV64-NEXT: # %bb.1: # %trueblock 346; RV64-NEXT: fsw fa5, 0(a0) 347; RV64-NEXT: .LBB9_2: # %falseblock 348; RV64-NEXT: ret 349 %negx = fneg float %x 350 %negz = fneg float %z 351 %a = call float @llvm.fma.f32(float %negx, float %y, float %negz) 352 store float %a, ptr %p1 353 br i1 %cond, label %trueblock, label %falseblock 354 355trueblock: 356 %negy = fneg float %y 357 %negz2 = fneg float %z 358 %b = call float @llvm.fma.f32(float %negy, float %x, float %negz2) 359 store float %b, ptr %p1 360 br label %falseblock 361 362falseblock: 363 ret void 364} 365 366define void @commute_fnmadd_f64(double %x, double %y, double %z, ptr %p1, ptr %p2, i1 zeroext %cond) { 367; RV32-LABEL: commute_fnmadd_f64: 368; RV32: # %bb.0: 369; RV32-NEXT: fnmadd.d fa5, fa0, fa1, fa2 370; RV32-NEXT: fsd fa5, 0(a0) 371; RV32-NEXT: beqz a2, .LBB10_2 372; RV32-NEXT: # %bb.1: # %trueblock 373; RV32-NEXT: fsd fa5, 0(a0) 374; RV32-NEXT: .LBB10_2: # %falseblock 375; RV32-NEXT: ret 376; 377; RV64-LABEL: commute_fnmadd_f64: 378; RV64: # %bb.0: 379; RV64-NEXT: fnmadd.d fa5, fa0, fa1, fa2 380; RV64-NEXT: fsd fa5, 0(a0) 381; RV64-NEXT: beqz a2, .LBB10_2 382; RV64-NEXT: # %bb.1: # %trueblock 383; RV64-NEXT: fsd fa5, 0(a0) 384; RV64-NEXT: .LBB10_2: # %falseblock 385; RV64-NEXT: ret 386 %negx = fneg double %x 387 %negz = fneg double %z 388 %a = call double @llvm.fma.f64(double %negx, double %y, double %negz) 389 store double %a, ptr %p1 390 br i1 %cond, label %trueblock, label %falseblock 391 392trueblock: 393 %negy = fneg double %y 394 %negz2 = fneg double %z 395 %b = call double @llvm.fma.f64(double %negy, double %x, double %negz2) 396 store double %b, ptr %p1 397 br label %falseblock 398 399falseblock: 400 ret void 401} 402 403define void @commute_fnmsub_f16(half %x, half %y, half %z, ptr %p1, ptr %p2, i1 zeroext %cond) { 404; RV32-LABEL: commute_fnmsub_f16: 405; RV32: # %bb.0: 406; RV32-NEXT: fnmsub.h fa5, fa0, fa1, fa2 407; RV32-NEXT: fsh fa5, 0(a0) 408; RV32-NEXT: beqz a2, .LBB11_2 409; RV32-NEXT: # %bb.1: # %trueblock 410; RV32-NEXT: fsh fa5, 0(a0) 411; RV32-NEXT: .LBB11_2: # %falseblock 412; RV32-NEXT: ret 413; 414; RV64-LABEL: commute_fnmsub_f16: 415; RV64: # %bb.0: 416; RV64-NEXT: fnmsub.h fa5, fa0, fa1, fa2 417; RV64-NEXT: fsh fa5, 0(a0) 418; RV64-NEXT: beqz a2, .LBB11_2 419; RV64-NEXT: # %bb.1: # %trueblock 420; RV64-NEXT: fsh fa5, 0(a0) 421; RV64-NEXT: .LBB11_2: # %falseblock 422; RV64-NEXT: ret 423 %negx = fneg half %x 424 %a = call half @llvm.fma.f16(half %negx, half %y, half %z) 425 store half %a, ptr %p1 426 br i1 %cond, label %trueblock, label %falseblock 427 428trueblock: 429 %negy = fneg half %y 430 %b = call half @llvm.fma.f16(half %negy, half %x, half %z) 431 store half %b, ptr %p1 432 br label %falseblock 433 434falseblock: 435 ret void 436} 437 438define void @commute_fnmsub_f32(float %x, float %y, float %z, ptr %p1, ptr %p2, i1 zeroext %cond) { 439; RV32-LABEL: commute_fnmsub_f32: 440; RV32: # %bb.0: 441; RV32-NEXT: fnmsub.s fa5, fa0, fa1, fa2 442; RV32-NEXT: fsw fa5, 0(a0) 443; RV32-NEXT: beqz a2, .LBB12_2 444; RV32-NEXT: # %bb.1: # %trueblock 445; RV32-NEXT: fsw fa5, 0(a0) 446; RV32-NEXT: .LBB12_2: # %falseblock 447; RV32-NEXT: ret 448; 449; RV64-LABEL: commute_fnmsub_f32: 450; RV64: # %bb.0: 451; RV64-NEXT: fnmsub.s fa5, fa0, fa1, fa2 452; RV64-NEXT: fsw fa5, 0(a0) 453; RV64-NEXT: beqz a2, .LBB12_2 454; RV64-NEXT: # %bb.1: # %trueblock 455; RV64-NEXT: fsw fa5, 0(a0) 456; RV64-NEXT: .LBB12_2: # %falseblock 457; RV64-NEXT: ret 458 %negx = fneg float %x 459 %a = call float @llvm.fma.f32(float %negx, float %y, float %z) 460 store float %a, ptr %p1 461 br i1 %cond, label %trueblock, label %falseblock 462 463trueblock: 464 %negy = fneg float %y 465 %b = call float @llvm.fma.f32(float %negy, float %x, float %z) 466 store float %b, ptr %p1 467 br label %falseblock 468 469falseblock: 470 ret void 471} 472 473define void @commute_fnmsub_f64(double %x, double %y, double %z, ptr %p1, ptr %p2, i1 zeroext %cond) { 474; RV32-LABEL: commute_fnmsub_f64: 475; RV32: # %bb.0: 476; RV32-NEXT: fnmsub.d fa5, fa0, fa1, fa2 477; RV32-NEXT: fsd fa5, 0(a0) 478; RV32-NEXT: beqz a2, .LBB13_2 479; RV32-NEXT: # %bb.1: # %trueblock 480; RV32-NEXT: fsd fa5, 0(a0) 481; RV32-NEXT: .LBB13_2: # %falseblock 482; RV32-NEXT: ret 483; 484; RV64-LABEL: commute_fnmsub_f64: 485; RV64: # %bb.0: 486; RV64-NEXT: fnmsub.d fa5, fa0, fa1, fa2 487; RV64-NEXT: fsd fa5, 0(a0) 488; RV64-NEXT: beqz a2, .LBB13_2 489; RV64-NEXT: # %bb.1: # %trueblock 490; RV64-NEXT: fsd fa5, 0(a0) 491; RV64-NEXT: .LBB13_2: # %falseblock 492; RV64-NEXT: ret 493 %negx = fneg double %x 494 %a = call double @llvm.fma.f64(double %negx, double %y, double %z) 495 store double %a, ptr %p1 496 br i1 %cond, label %trueblock, label %falseblock 497 498trueblock: 499 %negy = fneg double %y 500 %b = call double @llvm.fma.f64(double %negy, double %x, double %z) 501 store double %b, ptr %p1 502 br label %falseblock 503 504falseblock: 505 ret void 506} 507 508define void @commute_fadd_f16(half %x, half %y, ptr %p1, ptr %p2, i1 zeroext %cond) { 509; RV32-LABEL: commute_fadd_f16: 510; RV32: # %bb.0: 511; RV32-NEXT: fadd.h fa5, fa0, fa1 512; RV32-NEXT: fsh fa5, 0(a0) 513; RV32-NEXT: beqz a2, .LBB14_2 514; RV32-NEXT: # %bb.1: # %trueblock 515; RV32-NEXT: fsh fa5, 0(a0) 516; RV32-NEXT: .LBB14_2: # %falseblock 517; RV32-NEXT: ret 518; 519; RV64-LABEL: commute_fadd_f16: 520; RV64: # %bb.0: 521; RV64-NEXT: fadd.h fa5, fa0, fa1 522; RV64-NEXT: fsh fa5, 0(a0) 523; RV64-NEXT: beqz a2, .LBB14_2 524; RV64-NEXT: # %bb.1: # %trueblock 525; RV64-NEXT: fsh fa5, 0(a0) 526; RV64-NEXT: .LBB14_2: # %falseblock 527; RV64-NEXT: ret 528 %a = fadd half %x, %y 529 store half %a, ptr %p1 530 br i1 %cond, label %trueblock, label %falseblock 531 532trueblock: 533 %b = fadd half %y, %x 534 store half %b, ptr %p1 535 br label %falseblock 536 537falseblock: 538 ret void 539} 540 541define void @commute_fadd_f32(float %x, float %y, ptr %p1, ptr %p2, i1 zeroext %cond) { 542; RV32-LABEL: commute_fadd_f32: 543; RV32: # %bb.0: 544; RV32-NEXT: fadd.s fa5, fa0, fa1 545; RV32-NEXT: fsw fa5, 0(a0) 546; RV32-NEXT: beqz a2, .LBB15_2 547; RV32-NEXT: # %bb.1: # %trueblock 548; RV32-NEXT: fsw fa5, 0(a0) 549; RV32-NEXT: .LBB15_2: # %falseblock 550; RV32-NEXT: ret 551; 552; RV64-LABEL: commute_fadd_f32: 553; RV64: # %bb.0: 554; RV64-NEXT: fadd.s fa5, fa0, fa1 555; RV64-NEXT: fsw fa5, 0(a0) 556; RV64-NEXT: beqz a2, .LBB15_2 557; RV64-NEXT: # %bb.1: # %trueblock 558; RV64-NEXT: fsw fa5, 0(a0) 559; RV64-NEXT: .LBB15_2: # %falseblock 560; RV64-NEXT: ret 561 %a = fadd float %x, %y 562 store float %a, ptr %p1 563 br i1 %cond, label %trueblock, label %falseblock 564 565trueblock: 566 %b = fadd float %y, %x 567 store float %b, ptr %p1 568 br label %falseblock 569 570falseblock: 571 ret void 572} 573 574define void @commute_fadd_f64(double %x, double %y, ptr %p1, ptr %p2, i1 zeroext %cond) { 575; RV32-LABEL: commute_fadd_f64: 576; RV32: # %bb.0: 577; RV32-NEXT: fadd.d fa5, fa0, fa1 578; RV32-NEXT: fsd fa5, 0(a0) 579; RV32-NEXT: beqz a2, .LBB16_2 580; RV32-NEXT: # %bb.1: # %trueblock 581; RV32-NEXT: fsd fa5, 0(a0) 582; RV32-NEXT: .LBB16_2: # %falseblock 583; RV32-NEXT: ret 584; 585; RV64-LABEL: commute_fadd_f64: 586; RV64: # %bb.0: 587; RV64-NEXT: fadd.d fa5, fa0, fa1 588; RV64-NEXT: fsd fa5, 0(a0) 589; RV64-NEXT: beqz a2, .LBB16_2 590; RV64-NEXT: # %bb.1: # %trueblock 591; RV64-NEXT: fsd fa5, 0(a0) 592; RV64-NEXT: .LBB16_2: # %falseblock 593; RV64-NEXT: ret 594 %a = fadd double %x, %y 595 store double %a, ptr %p1 596 br i1 %cond, label %trueblock, label %falseblock 597 598trueblock: 599 %b = fadd double %y, %x 600 store double %b, ptr %p1 601 br label %falseblock 602 603falseblock: 604 ret void 605} 606 607define void @commute_feq_f16(half %x, half %y, ptr %p1, ptr %p2, i1 zeroext %cond) { 608; RV32-LABEL: commute_feq_f16: 609; RV32: # %bb.0: 610; RV32-NEXT: feq.h a1, fa0, fa1 611; RV32-NEXT: sb a1, 0(a0) 612; RV32-NEXT: beqz a2, .LBB17_2 613; RV32-NEXT: # %bb.1: # %trueblock 614; RV32-NEXT: sb a1, 0(a0) 615; RV32-NEXT: .LBB17_2: # %falseblock 616; RV32-NEXT: ret 617; 618; RV64-LABEL: commute_feq_f16: 619; RV64: # %bb.0: 620; RV64-NEXT: feq.h a1, fa0, fa1 621; RV64-NEXT: sb a1, 0(a0) 622; RV64-NEXT: beqz a2, .LBB17_2 623; RV64-NEXT: # %bb.1: # %trueblock 624; RV64-NEXT: sb a1, 0(a0) 625; RV64-NEXT: .LBB17_2: # %falseblock 626; RV64-NEXT: ret 627 %a = fcmp oeq half %x, %y 628 %b = zext i1 %a to i8 629 store i8 %b, ptr %p1 630 br i1 %cond, label %trueblock, label %falseblock 631 632trueblock: 633 %c = fcmp oeq half %y, %x 634 %d = zext i1 %c to i8 635 store i8 %d, ptr %p1 636 br label %falseblock 637 638falseblock: 639 ret void 640} 641 642define void @commute_feq_f32(float %x, float %y, ptr %p1, ptr %p2, i1 zeroext %cond) { 643; RV32-LABEL: commute_feq_f32: 644; RV32: # %bb.0: 645; RV32-NEXT: feq.s a1, fa0, fa1 646; RV32-NEXT: sb a1, 0(a0) 647; RV32-NEXT: beqz a2, .LBB18_2 648; RV32-NEXT: # %bb.1: # %trueblock 649; RV32-NEXT: sb a1, 0(a0) 650; RV32-NEXT: .LBB18_2: # %falseblock 651; RV32-NEXT: ret 652; 653; RV64-LABEL: commute_feq_f32: 654; RV64: # %bb.0: 655; RV64-NEXT: feq.s a1, fa0, fa1 656; RV64-NEXT: sb a1, 0(a0) 657; RV64-NEXT: beqz a2, .LBB18_2 658; RV64-NEXT: # %bb.1: # %trueblock 659; RV64-NEXT: sb a1, 0(a0) 660; RV64-NEXT: .LBB18_2: # %falseblock 661; RV64-NEXT: ret 662 %a = fcmp oeq float %x, %y 663 %b = zext i1 %a to i8 664 store i8 %b, ptr %p1 665 br i1 %cond, label %trueblock, label %falseblock 666 667trueblock: 668 %c = fcmp oeq float %y, %x 669 %d = zext i1 %c to i8 670 store i8 %d, ptr %p1 671 br label %falseblock 672 673falseblock: 674 ret void 675} 676 677define void @commute_feq_f64(double %x, double %y, ptr %p1, ptr %p2, i1 zeroext %cond) { 678; RV32-LABEL: commute_feq_f64: 679; RV32: # %bb.0: 680; RV32-NEXT: feq.d a1, fa0, fa1 681; RV32-NEXT: sb a1, 0(a0) 682; RV32-NEXT: beqz a2, .LBB19_2 683; RV32-NEXT: # %bb.1: # %trueblock 684; RV32-NEXT: sb a1, 0(a0) 685; RV32-NEXT: .LBB19_2: # %falseblock 686; RV32-NEXT: ret 687; 688; RV64-LABEL: commute_feq_f64: 689; RV64: # %bb.0: 690; RV64-NEXT: feq.d a1, fa0, fa1 691; RV64-NEXT: sb a1, 0(a0) 692; RV64-NEXT: beqz a2, .LBB19_2 693; RV64-NEXT: # %bb.1: # %trueblock 694; RV64-NEXT: sb a1, 0(a0) 695; RV64-NEXT: .LBB19_2: # %falseblock 696; RV64-NEXT: ret 697 %a = fcmp oeq double %x, %y 698 %b = zext i1 %a to i8 699 store i8 %b, ptr %p1 700 br i1 %cond, label %trueblock, label %falseblock 701 702trueblock: 703 %c = fcmp oeq double %y, %x 704 %d = zext i1 %c to i8 705 store i8 %d, ptr %p1 706 br label %falseblock 707 708falseblock: 709 ret void 710} 711