xref: /llvm-project/llvm/test/CodeGen/RISCV/machine-combiner.mir (revision 1aecb0e000e4efaa347e836e7ac06e070559dc2c) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
2# RUN: llc %s -o - -mtriple=riscv64 -mattr=+f -run-pass=machine-combiner \
3# RUN:   -verify-machineinstrs | FileCheck %s
4
5--- |
6  source_filename = "test.ll"
7  target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
8  target triple = "riscv64"
9
10  define void @foo(ptr %0, ptr %1, float %2, float %3, ptr %4, ptr %5) #0 {
11    %7 = load float, ptr %0, align 4
12    %8 = load float, ptr %1, align 4
13    %9 = fmul fast float %8, %7
14    %10 = fadd fast float %9, %2
15    store float %10, ptr %4, align 4
16    %11 = fsub fast float %3, %9
17    store float %11, ptr %5, align 4
18    ret void
19  }
20
21  attributes #0 = { "target-features"="+f" }
22
23...
24---
25name:            foo
26alignment:       4
27tracksRegLiveness: true
28registers:
29  - { id: 0, class: gpr }
30  - { id: 1, class: gpr }
31  - { id: 2, class: fpr32 }
32  - { id: 3, class: fpr32 }
33  - { id: 4, class: gpr }
34  - { id: 5, class: gpr }
35  - { id: 6, class: fpr32 }
36  - { id: 7, class: fpr32 }
37  - { id: 8, class: fpr32 }
38  - { id: 9, class: fpr32 }
39  - { id: 10, class: fpr32 }
40liveins:
41  - { reg: '$x10', virtual-reg: '%0' }
42  - { reg: '$x11', virtual-reg: '%1' }
43  - { reg: '$f10_f', virtual-reg: '%2' }
44  - { reg: '$f11_f', virtual-reg: '%3' }
45  - { reg: '$x12', virtual-reg: '%4' }
46  - { reg: '$x13', virtual-reg: '%5' }
47frameInfo:
48  maxAlignment:    1
49machineFunctionInfo:
50  varArgsFrameIndex: 0
51  varArgsSaveSize: 0
52body:             |
53  bb.0 (%ir-block.6):
54    liveins: $x10, $x11, $f10_f, $f11_f, $x12, $x13
55
56    ; CHECK-LABEL: name: foo
57    ; CHECK: liveins: $x10, $x11, $f10_f, $f11_f, $x12, $x13
58    ; CHECK-NEXT: {{  $}}
59    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
60    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
61    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $f11_f
62    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY $f10_f
63    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x11
64    ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr = COPY $x10
65    ; CHECK-NEXT: [[FLW:%[0-9]+]]:fpr32 = FLW [[COPY5]], 0 :: (load (s32) from %ir.0)
66    ; CHECK-NEXT: [[FLW1:%[0-9]+]]:fpr32 = FLW [[COPY4]], 0 :: (load (s32) from %ir.1)
67    ; CHECK-NEXT: [[FMADD_S:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FMADD_S [[FLW1]], [[FLW]], [[COPY3]], 7, implicit $frm
68    ; CHECK-NEXT: FSW killed [[FMADD_S]], [[COPY1]], 0 :: (store (s32) into %ir.4)
69    ; CHECK-NEXT: [[FNMSUB_S:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FNMSUB_S [[FLW1]], [[FLW]], [[COPY2]], 7, implicit $frm
70    ; CHECK-NEXT: FSW killed [[FNMSUB_S]], [[COPY]], 0 :: (store (s32) into %ir.5)
71    ; CHECK-NEXT: PseudoRET
72    %5:gpr = COPY $x13
73    %4:gpr = COPY $x12
74    %3:fpr32 = COPY $f11_f
75    %2:fpr32 = COPY $f10_f
76    %1:gpr = COPY $x11
77    %0:gpr = COPY $x10
78    %6:fpr32 = FLW %0, 0 :: (load (s32) from %ir.0)
79    %7:fpr32 = FLW %1, 0 :: (load (s32) from %ir.1)
80    %8:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FMUL_S killed %7, killed %6, 7, implicit $frm
81    %9:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADD_S %8, %2, 7, implicit $frm
82    FSW killed %9, %4, 0 :: (store (s32) into %ir.4)
83    %10:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FSUB_S %3, %8, 7, implicit $frm
84    FSW killed %10, %5, 0 :: (store (s32) into %ir.5)
85    PseudoRET
86
87...
88