1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=riscv32 -verify-machineinstrs -mattr=+m | FileCheck %s -check-prefixes=RV32 3; RUN: llc < %s -mtriple=riscv64 -verify-machineinstrs -mattr=+m | FileCheck %s -check-prefixes=RV64 4 5; Test case: 6; - Addition should be cheaper than multiplication 7 8; The following LLVM IR simulates: 9; int8_t flag2[8193]; 10; void test(int i) { 11; int tmp = i * 2; 12; if (i * 2 > 8192) return ; 13; for (int j = 0; ; ++j) { 14; int offset = j * i + tmp; 15; flag2[offset] = 0; 16; if (offset + i > 8192) break; 17; } 18; } 19 20; After LSR: 21; int8_t flag2[8193]; 22; void test(int i) { 23; int j = i * 2; 24; if (j > 8193) return ; 25; do { 26; flag2[j] = 0; 27; j += i; 28; } while (j < 8193); 29; } 30 31@flags2 = internal global [8193 x i8] zeroinitializer, align 32 ; <ptr> [#uses=1] 32 33define void @test(i32 signext %i) nounwind { 34; RV32-LABEL: test: 35; RV32: # %bb.0: # %entry 36; RV32-NEXT: slli a1, a0, 1 37; RV32-NEXT: lui a3, 2 38; RV32-NEXT: blt a3, a1, .LBB0_3 39; RV32-NEXT: # %bb.1: # %bb.preheader 40; RV32-NEXT: lui a2, %hi(flags2) 41; RV32-NEXT: addi a2, a2, %lo(flags2) 42; RV32-NEXT: addi a3, a3, 1 43; RV32-NEXT: .LBB0_2: # %bb 44; RV32-NEXT: # =>This Inner Loop Header: Depth=1 45; RV32-NEXT: add a4, a2, a1 46; RV32-NEXT: add a1, a1, a0 47; RV32-NEXT: sb zero, 0(a4) 48; RV32-NEXT: blt a1, a3, .LBB0_2 49; RV32-NEXT: .LBB0_3: # %return 50; RV32-NEXT: ret 51; 52; RV64-LABEL: test: 53; RV64: # %bb.0: # %entry 54; RV64-NEXT: slliw a1, a0, 1 55; RV64-NEXT: lui a3, 2 56; RV64-NEXT: blt a3, a1, .LBB0_3 57; RV64-NEXT: # %bb.1: # %bb.preheader 58; RV64-NEXT: lui a2, %hi(flags2) 59; RV64-NEXT: addi a2, a2, %lo(flags2) 60; RV64-NEXT: addiw a3, a3, 1 61; RV64-NEXT: .LBB0_2: # %bb 62; RV64-NEXT: # =>This Inner Loop Header: Depth=1 63; RV64-NEXT: slli a4, a1, 32 64; RV64-NEXT: srli a4, a4, 32 65; RV64-NEXT: add a4, a2, a4 66; RV64-NEXT: addw a1, a1, a0 67; RV64-NEXT: sb zero, 0(a4) 68; RV64-NEXT: blt a1, a3, .LBB0_2 69; RV64-NEXT: .LBB0_3: # %return 70; RV64-NEXT: ret 71entry: 72 %k_addr.012 = shl i32 %i, 1 73 %tmp14 = icmp sgt i32 %k_addr.012, 8192 74 br i1 %tmp14, label %return, label %bb 75 76bb: 77 %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] 78 %tmp.15 = mul i32 %indvar, %i 79 %tmp.16 = add i32 %tmp.15, %k_addr.012 80 %gep.upgrd.1 = zext i32 %tmp.16 to i64 81 %tmp = getelementptr [8193 x i8], ptr @flags2, i32 0, i64 %gep.upgrd.1 82 store i8 0, ptr %tmp 83 %tmp.17 = add i32 %tmp.16, %i 84 %tmp.upgrd.2 = icmp sgt i32 %tmp.17, 8192 85 %indvar.next = add i32 %indvar, 1 86 br i1 %tmp.upgrd.2, label %return, label %bb 87 88return: 89 ret void 90} 91