xref: /llvm-project/llvm/test/CodeGen/RISCV/load-setcc-combine.ll (revision d5167c84f9eddf6a37c667d4673bf694dfd8be37)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
3
4define i8 @zext_nonneg_load_i16(ptr %x, ptr %y) {
5; CHECK-LABEL: zext_nonneg_load_i16:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    lh a0, 0(a0)
8; CHECK-NEXT:    bltz a0, .LBB0_2
9; CHECK-NEXT:  # %bb.1: # %cont
10; CHECK-NEXT:    add a0, a1, a0
11; CHECK-NEXT:    lbu a0, 0(a0)
12; CHECK-NEXT:    ret
13; CHECK-NEXT:  .LBB0_2: # %exit
14; CHECK-NEXT:    li a0, 0
15; CHECK-NEXT:    ret
16  %a = load i16, ptr %x
17  %b = icmp slt i16 %a, 0
18  br i1 %b, label %exit, label %cont
19
20cont:
21  %c = zext nneg i16 %a to i64
22  %d = getelementptr i8, ptr %y, i64 %c
23  %e = load i8, ptr %d
24  ret i8 %e
25
26exit:
27  ret i8 0
28}
29