1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc -mtriple=riscv32 -mattr=+zdinx -target-abi=ilp32 -verify-machineinstrs < %s \ 3; RUN: | FileCheck -check-prefix=RV32FINX %s 4; RUN: llc -mtriple=riscv64 -mattr=+zdinx -target-abi=lp64 -verify-machineinstrs < %s \ 5; RUN: | FileCheck -check-prefix=RV64FINX %s 6 7@gd = external global double 8 9define double @constraint_r_double(double %a) nounwind { 10; RV32FINX-LABEL: constraint_r_double: 11; RV32FINX: # %bb.0: 12; RV32FINX-NEXT: lui a2, %hi(gd) 13; RV32FINX-NEXT: lw a3, %lo(gd+4)(a2) 14; RV32FINX-NEXT: lw a2, %lo(gd)(a2) 15; RV32FINX-NEXT: #APP 16; RV32FINX-NEXT: fadd.d a0, a0, a2 17; RV32FINX-NEXT: #NO_APP 18; RV32FINX-NEXT: ret 19; 20; RV64FINX-LABEL: constraint_r_double: 21; RV64FINX: # %bb.0: 22; RV64FINX-NEXT: lui a1, %hi(gd) 23; RV64FINX-NEXT: ld a1, %lo(gd)(a1) 24; RV64FINX-NEXT: #APP 25; RV64FINX-NEXT: fadd.d a0, a0, a1 26; RV64FINX-NEXT: #NO_APP 27; RV64FINX-NEXT: ret 28 %1 = load double, ptr @gd 29 %2 = tail call double asm "fadd.d $0, $1, $2", "=r,r,r"(double %a, double %1) 30 ret double %2 31} 32 33define double @constraint_cr_double(double %a) nounwind { 34; RV32FINX-LABEL: constraint_cr_double: 35; RV32FINX: # %bb.0: 36; RV32FINX-NEXT: lui a2, %hi(gd) 37; RV32FINX-NEXT: lw a3, %lo(gd+4)(a2) 38; RV32FINX-NEXT: lw a2, %lo(gd)(a2) 39; RV32FINX-NEXT: #APP 40; RV32FINX-NEXT: fadd.d a0, a0, a2 41; RV32FINX-NEXT: #NO_APP 42; RV32FINX-NEXT: ret 43; 44; RV64FINX-LABEL: constraint_cr_double: 45; RV64FINX: # %bb.0: 46; RV64FINX-NEXT: lui a1, %hi(gd) 47; RV64FINX-NEXT: ld a1, %lo(gd)(a1) 48; RV64FINX-NEXT: #APP 49; RV64FINX-NEXT: fadd.d a0, a0, a1 50; RV64FINX-NEXT: #NO_APP 51; RV64FINX-NEXT: ret 52 %1 = load double, ptr @gd 53 %2 = tail call double asm "fadd.d $0, $1, $2", "=^cr,^cr,^cr"(double %a, double %1) 54 ret double %2 55} 56 57define double @constraint_double_abi_name(double %a) nounwind { 58; RV32FINX-LABEL: constraint_double_abi_name: 59; RV32FINX: # %bb.0: 60; RV32FINX-NEXT: addi sp, sp, -16 61; RV32FINX-NEXT: sw s0, 12(sp) # 4-byte Folded Spill 62; RV32FINX-NEXT: sw s1, 8(sp) # 4-byte Folded Spill 63; RV32FINX-NEXT: lui a2, %hi(gd) 64; RV32FINX-NEXT: lw s0, %lo(gd)(a2) 65; RV32FINX-NEXT: lw s1, %lo(gd+4)(a2) 66; RV32FINX-NEXT: #APP 67; RV32FINX-NEXT: fadd.d t1, a0, s0 68; RV32FINX-NEXT: #NO_APP 69; RV32FINX-NEXT: mv a0, t1 70; RV32FINX-NEXT: mv a1, t2 71; RV32FINX-NEXT: lw s0, 12(sp) # 4-byte Folded Reload 72; RV32FINX-NEXT: lw s1, 8(sp) # 4-byte Folded Reload 73; RV32FINX-NEXT: addi sp, sp, 16 74; RV32FINX-NEXT: ret 75; 76; RV64FINX-LABEL: constraint_double_abi_name: 77; RV64FINX: # %bb.0: 78; RV64FINX-NEXT: addi sp, sp, -16 79; RV64FINX-NEXT: sd s0, 8(sp) # 8-byte Folded Spill 80; RV64FINX-NEXT: lui a1, %hi(gd) 81; RV64FINX-NEXT: ld s0, %lo(gd)(a1) 82; RV64FINX-NEXT: #APP 83; RV64FINX-NEXT: fadd.d t1, a0, s0 84; RV64FINX-NEXT: #NO_APP 85; RV64FINX-NEXT: mv a0, t1 86; RV64FINX-NEXT: ld s0, 8(sp) # 8-byte Folded Reload 87; RV64FINX-NEXT: addi sp, sp, 16 88; RV64FINX-NEXT: ret 89 %1 = load double, ptr @gd 90 %2 = tail call double asm "fadd.d $0, $1, $2", "={t1},{a0},{s0}"(double %a, double %1) 91 ret double %2 92} 93 94define double @constraint_f_double(double %a) nounwind { 95; RV32FINX-LABEL: constraint_f_double: 96; RV32FINX: # %bb.0: 97; RV32FINX-NEXT: lui a2, %hi(gd) 98; RV32FINX-NEXT: lw a3, %lo(gd+4)(a2) 99; RV32FINX-NEXT: lw a2, %lo(gd)(a2) 100; RV32FINX-NEXT: #APP 101; RV32FINX-NEXT: fadd.d a0, a0, a2 102; RV32FINX-NEXT: #NO_APP 103; RV32FINX-NEXT: ret 104; 105; RV64FINX-LABEL: constraint_f_double: 106; RV64FINX: # %bb.0: 107; RV64FINX-NEXT: lui a1, %hi(gd) 108; RV64FINX-NEXT: ld a1, %lo(gd)(a1) 109; RV64FINX-NEXT: #APP 110; RV64FINX-NEXT: fadd.d a0, a0, a1 111; RV64FINX-NEXT: #NO_APP 112; RV64FINX-NEXT: ret 113 %1 = load double, ptr @gd 114 %2 = tail call double asm "fadd.d $0, $1, $2", "=f,f,f"(double %a, double %1) 115 ret double %2 116} 117 118define double @constraint_cf_double(double %a) nounwind { 119; RV32FINX-LABEL: constraint_cf_double: 120; RV32FINX: # %bb.0: 121; RV32FINX-NEXT: lui a2, %hi(gd) 122; RV32FINX-NEXT: lw a3, %lo(gd+4)(a2) 123; RV32FINX-NEXT: lw a2, %lo(gd)(a2) 124; RV32FINX-NEXT: #APP 125; RV32FINX-NEXT: fadd.d a0, a0, a2 126; RV32FINX-NEXT: #NO_APP 127; RV32FINX-NEXT: ret 128; 129; RV64FINX-LABEL: constraint_cf_double: 130; RV64FINX: # %bb.0: 131; RV64FINX-NEXT: lui a1, %hi(gd) 132; RV64FINX-NEXT: ld a1, %lo(gd)(a1) 133; RV64FINX-NEXT: #APP 134; RV64FINX-NEXT: fadd.d a0, a0, a1 135; RV64FINX-NEXT: #NO_APP 136; RV64FINX-NEXT: ret 137 %1 = load double, ptr @gd 138 %2 = tail call double asm "fadd.d $0, $1, $2", "=^cf,^cf,^cf"(double %a, double %1) 139 ret double %2 140} 141