xref: /llvm-project/llvm/test/CodeGen/RISCV/inline-asm-f-modifier-N.ll (revision 228f88fdc8e92789e0562f8a47493493da843145)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs -no-integrated-as < %s \
3; RUN:   | FileCheck -check-prefix=RV32F %s
4; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs -no-integrated-as < %s \
5; RUN:   | FileCheck -check-prefix=RV64F %s
6; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs -no-integrated-as < %s \
7; RUN:   | FileCheck -check-prefix=RV32F %s
8; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs -no-integrated-as < %s \
9; RUN:   | FileCheck -check-prefix=RV64F %s
10
11;; `.insn 0x4, 0x53 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)` is
12;; the raw encoding for `fadd.s`
13
14@gf = external global float
15
16define float @constraint_f_modifier_N_float(float %a) nounwind {
17; RV32F-LABEL: constraint_f_modifier_N_float:
18; RV32F:       # %bb.0:
19; RV32F-NEXT:    lui a1, %hi(gf)
20; RV32F-NEXT:    flw fa5, %lo(gf)(a1)
21; RV32F-NEXT:    fmv.w.x fa4, a0
22; RV32F-NEXT:    #APP
23; RV32F-NEXT:    .insn 0x4, 0x53 | (15 << 7) | (14 << 15) | (15 << 20)
24; RV32F-NEXT:    #NO_APP
25; RV32F-NEXT:    fmv.x.w a0, fa5
26; RV32F-NEXT:    ret
27;
28; RV64F-LABEL: constraint_f_modifier_N_float:
29; RV64F:       # %bb.0:
30; RV64F-NEXT:    lui a1, %hi(gf)
31; RV64F-NEXT:    flw fa5, %lo(gf)(a1)
32; RV64F-NEXT:    fmv.w.x fa4, a0
33; RV64F-NEXT:    #APP
34; RV64F-NEXT:    .insn 0x4, 0x53 | (15 << 7) | (14 << 15) | (15 << 20)
35; RV64F-NEXT:    #NO_APP
36; RV64F-NEXT:    fmv.x.w a0, fa5
37; RV64F-NEXT:    ret
38  %1 = load float, ptr @gf
39  %2 = tail call float asm ".insn 0x4, 0x53 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "=f,f,f"(float %a, float %1)
40  ret float %2
41}
42
43
44define float @constraint_cf_modifier_N_float(float %a) nounwind {
45; RV32F-LABEL: constraint_cf_modifier_N_float:
46; RV32F:       # %bb.0:
47; RV32F-NEXT:    lui a1, %hi(gf)
48; RV32F-NEXT:    flw fa5, %lo(gf)(a1)
49; RV32F-NEXT:    fmv.w.x fa4, a0
50; RV32F-NEXT:    #APP
51; RV32F-NEXT:    .insn 0x4, 0x53 | (15 << 7) | (14 << 15) | (15 << 20)
52; RV32F-NEXT:    #NO_APP
53; RV32F-NEXT:    fmv.x.w a0, fa5
54; RV32F-NEXT:    ret
55;
56; RV64F-LABEL: constraint_cf_modifier_N_float:
57; RV64F:       # %bb.0:
58; RV64F-NEXT:    lui a1, %hi(gf)
59; RV64F-NEXT:    flw fa5, %lo(gf)(a1)
60; RV64F-NEXT:    fmv.w.x fa4, a0
61; RV64F-NEXT:    #APP
62; RV64F-NEXT:    .insn 0x4, 0x53 | (15 << 7) | (14 << 15) | (15 << 20)
63; RV64F-NEXT:    #NO_APP
64; RV64F-NEXT:    fmv.x.w a0, fa5
65; RV64F-NEXT:    ret
66  %1 = load float, ptr @gf
67  %2 = tail call float asm ".insn 0x4, 0x53 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "=^cf,^cf,^cf"(float %a, float %1)
68  ret float %2
69}
70
71define float @modifier_N_float_abi_name(float %a) nounwind {
72; RV32F-LABEL: modifier_N_float_abi_name:
73; RV32F:       # %bb.0:
74; RV32F-NEXT:    lui a1, %hi(gf)
75; RV32F-NEXT:    flw fs0, %lo(gf)(a1)
76; RV32F-NEXT:    fmv.w.x fa0, a0
77; RV32F-NEXT:    #APP
78; RV32F-NEXT:    .insn 0x4, 0x53 | (0 << 7) | (10 << 15) | (8 << 20)
79; RV32F-NEXT:    #NO_APP
80; RV32F-NEXT:    fmv.x.w a0, ft0
81; RV32F-NEXT:    ret
82;
83; RV64F-LABEL: modifier_N_float_abi_name:
84; RV64F:       # %bb.0:
85; RV64F-NEXT:    lui a1, %hi(gf)
86; RV64F-NEXT:    flw fs0, %lo(gf)(a1)
87; RV64F-NEXT:    fmv.w.x fa0, a0
88; RV64F-NEXT:    #APP
89; RV64F-NEXT:    .insn 0x4, 0x53 | (0 << 7) | (10 << 15) | (8 << 20)
90; RV64F-NEXT:    #NO_APP
91; RV64F-NEXT:    fmv.x.w a0, ft0
92; RV64F-NEXT:    ret
93  %1 = load float, ptr @gf
94  %2 = tail call float asm ".insn 0x4, 0x53 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "={ft0},{fa0},{fs0}"(float %a, float %1)
95  ret float %2
96}
97